搜索资源列表
vhdl
- 输入为八位十进制数，用bcd码表示，还有平率技术函数
Mean_64
- 原创代码，采用VHDL实现的64点均值滤波。实验测试过，效果良好。可轻松修改成任意点数均值滤波。采用了多点滑动运算，减小了输出延时，最大为3个时钟延迟。可用于AD采样后的滤波处理。
usb_xilinx
- usb的接口资料，vhdl
usb
- 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码
iic_vhdl
- iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC u
VHDLrs232接口
- 简单易用的232接口 基于VHDL语言
VGA显示
- VGA的VHDL语言
qpsk.rar
- 载波同步是QPSK信号相干解调的一项关键技术。,Carrier synchronization signal coherent QPSK demodulation is a key technology.
uart.rar
- 实现串并口通信,共有发送和接受两个模块。,Strings parallel to achieve communication, send and receive a total of two modules.
code_dco.rar
- 通信电路中产生扩频码的电路，应用于GPS中的跟踪和捕获．,Communication circuit of the circuit generated spreading codes used in GPS tracking and capture.
ppmVHDL.rar
- 红外数据传输速率为4Mbit/s时的编解码4PPM，用vhdl实现的源代码，,Infrared data transfer rate of 4Mbit/s when the codec 4PPM, using VHDL implementation of the source code,
liuVHDL.rar
- 一种基于状态机设计的串并行转换电路，将LTC1196(ADC)的串行输出数据转换成并行数据的转换电路， ADC的时钟由转换电路提供，,Design a state machine based on parallel conversion circuit of the series will be LTC1196 (ADC) output of the serial data into parallel data conversion circuit, ADC clock provided by
wb_lpc_latest.tar.gz
- Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided.
decode.rar
- LDPC的Verilog程序源代码，包括仿真数据等。文件很大，请慢慢下载,LDPC of Verilog source code, including the simulation data. Large file, please download slowly
FPGA-OFDM-communication-system
- 基于ofdm系统的各个模块的VHDL程序，软件是用的ISE仿真的。绝对有用。-Ofdm systems based on VHDL program of each module, the software is to use the ISE simulation. Absolutely useful.
CIC.rar
- CIC梳状滤波器verilog源码，包括积分器，下抽级以及梳状滤波器三个部分。,CIC comb filter verilog source code, including the integrator, under the pump, as well as comb filter class is in three parts.
spi
- SPI master的verilog代码-Verilog code for SPI master
bch9.1
- 这是我做的一个BCH译码模块硬件语言模块，这么好的东西上传上来还不让下载-This is what I do a BCH decoding hardware module language module, so good things do not let up upload download
I-rife
- 频率估计，是一种比较简单的算法，很基础，有助于初学者应用-Frequency estimation, is a relatively simple algorithm, it is based applications to help beginners