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liuVHDL.rar
- 一种基于状态机设计的串并行转换电路，将LTC1196(ADC)的串行输出数据转换成并行数据的转换电路， ADC的时钟由转换电路提供，,Design a state machine based on parallel conversion circuit of the series will be LTC1196 (ADC) output of the serial data into parallel data conversion circuit, ADC clock provided by
uart
- 串口通讯rs232,时钟频率为40Mhz,波特率为19200,没有奇偶校验,在xilinx XC3S200A板子上验证过.-Serial communication rs232, clock frequency of 40Mhz, the baud rate to 19200, no parity, in the board on xilinx XC3S200A verified.
filter
- 时钟滤波器设计，可进行毛刺去除，有需要可依进行参考设计-Clock filter design can be carried out burr removed, there is a need-based reference design
liuVHDL
- 一种基于状态机设计的串并行转换电路，将LTC1196(ADC)的串行输出数据转换成并行数据的转换电路， ADC的时钟由转换电路提供，-Design a state machine based on parallel conversion circuit of the series will be LTC1196 (ADC) output of the serial data into parallel data conversion circuit, ADC clock provided by
pll
- 一个实现任意倍频的，输入参考频率未知的pll，已综合实现-frequency multiple rely on dpll，unknown reference input clock
clock
- 由锁相环(PLL)产生所需的2分频与4分频时钟8分频时钟 clk.qpf为可执行主程序 -By the phase-locked loop (PLL) have the necessary 2-and 4-frequency clock frequency of 8 minutes for Executable clk.qpf main clock
gmsk_2
- 实现2M数据速率的GMSK调制，时钟频率20M，2分频后作为移位寄存器-2M data rate to achieve the GMSK modulation, the clock frequency of 20M, 2 minutes after a shift register frequency
dualram
- VHDL Dual Clock Synchronous RAM Design
shuzizhong3
- 数字钟VHDL软件设计，包含多种功能，报时，12,24切换，调时-The design of VHDL digital clock software, including a variety of functions, timer, 12,24 switch, adjustable