搜索资源列表
rs
- rs编解码，对实现了rs码的编解码，并对其误码率进行了分析仿真-rs codec, to the achievement of the rs code coding and decoding, and BER analysis simulation
Xilinx-FPGA-Matlab-Simulate
- Xilinx的FPGA 中的matlab simulink建模，内有几种调制方式，比如QPSK等-Xilinx
Lab10_RS232_ise10migration
- 串口传输,通过XILINX FPGA使用串口进行数据的接收和发送-RS232
SerialPort
- 一个用verilog HDL 编写的串口发送程序，可以下载到FPGA中。已经在ActelFPGA中试过了，很好用。稍微修改之后，可以与Xilinx和Altera公司的FPGA兼容。-A programe dialogue to transmit a serial data which is writen by Verilog HDL.
src
- DQPSK modulation with XILINX FPGA. 2 level butterworth analog filter for I & Q D/A output. -DQPSK modulation with XILINX FPGA. 2 level butterworth analog filter for I & Q D/A output.
core_licenses_full
- 这个是XILINX公司FPGA的aurora，IP授权！！完全好用!-This is the XILINX' s FPGA-aurora, IP licensing! ! Totally easy to use!
high_speed_data_recovery
- 1. 程序的功能是:高速串行数据的恢复. 2. 其基本原理是：利用过采样，检测串行数据的边沿跳变，然后根据边沿提取处在数据相位正中央相邻的抽样值，将串行数据恢复过来。 3. 此程序是verilog 语言编写，用于xilinx virtexE 系列的FPGA-1. Program functions are: high-speed serial data recovery. 2. The basic principle is: the use of over-sampling to det
HDLC_VHDL
- 用VHDL实现从以太网到并行数据以及从并行数据到以太网的HDLC成帧解帧.附详细代码说明,方便阅读.可方面移植到Altera及Xilinx等厂家芯片,是做基于FPGA的以太网设计的好资料-Achieved using VHDL and parallel data from the Ethernet to parallel data from the HDLC framing solution to Ethernet frames. Attached detailed code instructi
fpga_mcu_uart
- 用FPGA 开发板 SPARTAN3实现的串口程序，用XILINX 自带的ip核 -Achieved with the FPGA development board SPARTAN3 serial program that comes with the ip nuclear XILINX
usb-fpga-1.2
- USB Tranfer using libusb ready in Java. Automatically flashes FPGA (for Xilinx Spartan 6) and starts USB-process.
USB_project
- USB interface FPGA USB: CY680013CA FPGA: Xilinx, Altera
uart
- Code VHDL/Verilog for UART FPGA: Xilinx, Altera-Code VHDL/Verilog for UART FPGA: Xilinx, Altera...
dsp-presentation
- xilinx提供的用于数字信号处理开发的FPGA资料。-xilinx FPGA DSP
dsp_flow
- xilinx提供的用于数字信号处理开发的FPGA资料。-xilinx FPGA DSP
xilinx-fpga-ofdm
- 基于XILINX FPGA的OFDM通信系统基带设计-xilinx fpga OFDM
34
- TD-SCDMA的长期演进TD-LTE。为减轻TD-LTE综测仪开发中调试的复杂性，通过研究分析TD-LTE系统原语，提出了一种基于DSP TMS320C6455和FPGA 5vsx95tff1136(Xilinx)芯片的原语追踪平台。-Long-term evolution of TD-SCDMA, TD-LTE. TD-LTE system primitives through research and analysis in order to reduce the complexity o
maopao
- TD-SCDMA的长期演进TD-LTE。为减轻TD-LTE综测仪开发中调试的复杂性，通过研究分析TD-LTE系统原语，提出了一种基于DSP TMS320C6455和FPGA 5vsx95tff1136(Xilinx)芯片的原语追踪平台。-Long-term evolution of TD-SCDMA, TD-LTE. TD-LTE system primitives through research and analysis in order to reduce the complexity o
paixufahanshu
- TD-SCDMA的长期演进TD-LTE。为减轻TD-LTE综测仪开发中调试的复杂性，通过研究分析TD-LTE系统原语，提出了一种基于DSP TMS320C6455和FPGA 5vsx95tff1136(Xilinx)芯片的原语追踪平台。-Long-term evolution of TD-SCDMA, TD-LTE. TD-LTE system primitives through research and analysis in order to reduce the complexity o
sushu1
- TD-SCDMA的长期演进TD-LTE。为减轻TD-LTE综测仪开发中调试的复杂性，通过研究分析TD-LTE系统原语，提出了一种基于DSP TMS320C6455和FPGA 5vsx95tff1136(Xilinx)芯片的原语追踪平台。-Long-term evolution of TD-SCDMA, TD-LTE. TD-LTE system primitives through research and analysis in order to reduce the complexity o
groundhog_v_0_2
- Groundhog implements a SATA host bus adapter.-Groundhog implements a SATA host bus adapter. This Verilog-based project creates an easy-to-use interface between a user circuit on a Xilinx FPGA and a SATA hard drive or SSD.