此代码可实现8bits 108M 4路BT656 像素交织输入转为8bits 108M 4路行交织的视频数据，并有仿真文件，在modelsim中运行即可。-This code can be realized 8bits 108M 4 way BT656 pixel interleaving input into 8bits 108M 4 way line of cutting the video data, and there are simulation files can be run in

图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过-Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by

OV5620 VHDL CODE, Alter FPGA Source Code.

包含了用Spartan6控制OV7670的VHDL源程序，以及PC上的测试程序。对于学习EZUSB的朋友很有帮助。-OV7670 includes the use Spartan6 control of VHDL source code, and test program on the PC. EZUSB for learning helpful friends.