搜索资源列表
mcudesigne
- msp各个模块源码 如定时器，COM，硬件乘法器比较器USART,ADC.
64位乘法器verilog
- 64位乘法器的源码，测试代码以及详细的报告
alu
- 描述乘法器，组成原理vhdl实现一位乘法器程序代码-Describe the multiplier, the composition principle to achieve a multiplier vhdl code
module-multiplier
- 用vhdl编程，实现了一个2^N+1模乘法器，经验证，设计结果完全正确-use the vhdl language to design a module 2^n+1 multiplier
Hardware_Multiplier
- 利用MSP430F149内部的硬件乘法器进行8bit-8bit，16bit-16bit的乘法，只需三个主时钟周期，即可读出运算结果。-Using MSP430F149 internal hardware multiplier for 8bit-8bit, 16bit-16bit multiplication, just three master clock cycles, you can read out the result of the operation.
MSP430x261x_MPY
- MSP430x261x 硬件乘法器配置程序-MSP430x261x hardware multiplier configuration program
booth-multiplier
- 布斯乘法器设计源码。。功能完善，modelsim仿真通过-Booth Multiplier source. . Perfect function, modelsim simulation through
16 bit signed number multiplier
- 16位有符号数乘法器，使用Booth编码和华莱士树，提供程序源文件和测试文件(The 16 bit signed multiplier uses Booth encoding and Wallace tree to provide source files and test files.)