A full-parallel architecture for turbo decoding, which achieves ultrahigh data rates when using product codes as error correcting codes, is proposed. This architecture is able to decode product codes using binary BCH or m-ary Reed-Solomon compo

BRCM 平台ECC算法(C语言),该算法可以产生3字节的ECC,每512字节一组-BRCM NAND Flesh Memory ECC Encoder (Hamming code and BCH codes)