搜索资源列表
counter_7seg
- 带分频器的bcd计数电路设计，verilog源码-dividers with the bcd count circuit design, Verilog source
div5
- 简单的VERILOG五分频电路描述，可综合。已经过检验-simple verilog 0.2-frequency circuit descr iption can be integrated. Have been tested
clkgen
- 用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280分频.
fp_2
- 通过Verilog HDL编程，在CPLD上实现任意小数（分数）分频，分频系数为N+A/B.-By Verilog HDL programming, to achieve any decimal in the CPLD (score) frequency, frequency coefficient N+ A/B.
fen-pin-Verilog(2013-06-25-09.54.41)
- 任意小数分频，适用于对精确度要求不高的代码中-Any fractional divider, suitable for less demanding precision code
Taximeter
- 出租车计价器（其中包括分频模块，计程模块，计时模块，计费模块，显示模块以及顶层模块），基于Verilog HDL语言，开发板是FPGA(Sparten 6 LXS45),开发环境是Xilinx。-Taxi meter (including frequency module, the meter module, timing module, billing module, display module and top-level module), based on Verilog HDL lang