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verilog的源代码。给出来常用的一些例程，对于verilog的使用和学习都有很大的帮助作用。-Verilog source code. Out to some routines commonly used for the use and Verilog study has been very helpful.
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基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
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本文件是pci的verilog源代码程序-pci the Verilog source code procedures
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用verilog语言编写的全数字锁相环的源代码,基于fpga平台-using Verilog language prepared by the DPLL the source code, they simply based on the platform
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发一个基于ModelSim仿真的Verilog源代码包-made a ModelSim simulation based on the Verilog source code
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Xilinx EDK中SOC使用外部存储器接口（EMC）的方法，并用ISP1581举例说明了如何与时分复用总线（8051单片机总线）设备进行连接，有Verilog源代码。,Xilinx EDK in SOC using external memory interface (EMC) methods, and examples of how ISP1581 with the TDM bus (8051 bus) devices to connect, there Verilog source co
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This OVM 2.0 source code .Very useful for developing system verilog Env-This is OVM 2.0 source code .Very useful for developing system verilog Env
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对串行输入的数据流进行检测的ＶＥＲＩＬＯＧ源代码-On the serial input data streams to detect the Verilog source code
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EDA设计源代码，verilog计算器设计-EDA design source code, verilog calculator design
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verilog语言编写的交通灯程序源代码-the Verilog language of traffic lights program source code
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本例程位于 VMD642_CPLD目录中。
使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使
用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。-This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and othe
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一个verilog时钟发生器源代码，能够满足最小时间间隔0.1ns的时钟计时要求。-A clock generator verilog source code, to meet the minimum time interval of 0.1ns clock timing requirements.
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一个用Verilog语言编写的SDRAM控制器源码, 逻辑清晰, 结构合理!-SDRAM controller is a source code in Verilog language, logical, reasonable structure!
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SD卡读写源代码.用Verilog编写.很不错.值得借鉴.特别对SD卡开发的人员!--SD card reader-writer source code. Prepared to use Verilog. Is pretty good. Be used for reference. In particular, the development of personnel SD card!
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ADI公司ADF4350频率源芯片的verilog程序源代码，之前做过一个项目中的一部分，现在把代码拿来与大家分享-ADI' s ADF4350 frequency source chip verilog source code, done before a project part, and now the code is used to share with everyone
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It is a Verilog code for SPI master. It includes source code and a testbench to test the functionality.-It is a Verilog code for SPI master. It includes source code and a testbench to test the functionality.
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自己总结的Altera_LVDS的IP核的设计及仿真分析，已在实际工程中应用到，并且带有源代码和仿真代码，总结的文档，非常有用。(My summary of the Altera_LVDS IP kernel design and simulation analysis, has been applied in practical engineering, and with source code and simulation code, summary of the document, ver
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