数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法-Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis

DAC IC AD9708Driver code,use verilog hdl,Can output sine wave, cosine wave

verilog教程，更加偏向工程化的verilog实用教程，有很多实际模块，推荐(Verilog tutorial, more biased toward the engineering of the Verilog practical tutorial, there are many practical modules, recommended)