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MCGSsoftwareconfigurationofnetworkequipmenthardwar
- MCGS组态软件的网络设备硬件驱动,包括网络事件处理、网络数据库同步和网络数据同步!可实现网络设备与上位机的连接-MCGS software configuration of network equipment hardware drivers, including network event handling, web-based database synchronization and data synchronization network! Network equipment can b
signal
- 产生编码解码时使用的clk_1以及频率为它31倍的clk_31信号。 //产生M序列的发送信号indata(随机),并且将接收到的解码信号(decode)进行比较。 //发送的头10个信号为1,第11个为0,在解码的开始时期进行同步判断时用到。-Have used codec clk_1 as well as the frequency of 31 times it clk_31 signal.// Generate the M sequence signal indata (rando
decode
- //接收端的解码模块(可综合) //在信号接收的刚开始发送端发送的是10个1信号, //即10个+M序列,所以我们在开始时每接收到一个信号做一次累加运算 //当出现正的高峰时则认为达到同步,进入同步解调过程(mainbody)。 //也就是从此每进入一个信号就进行相应的相乘相加, //在解接收到31个信号后进行一次判断,大于0认为接收到1,小于0认为接收到0。-//Receiver decoder module (which can be integrated)// at t
mcn_sy4
- (1)通过开关K0合上与断开控制A/D转换的开始和停止,当开始A/D转换后,每秒对连接到PTB3的模拟量采样一次,结果送指示灯D7~D0显示。 (2)采样结果同步通过串行接口发送到PC机(38400bps,N,8,1),显示格式为“The signal is:x.xV”(满量程为5.0V)。 -(1) through the closed switch and disconnect K0 control A/D conversion start and stop, when to st
vheader
- 将VHDL源文件中提取常量转换成C/C++的头文件。用于VHDL的固件和主机程序间的同步,如:寄存器地址,缓冲区长度,版本号等。-This short program converts the constants in VHDL files into C/C++ header files. It is useful to sync the VHDL firmware and C/C++ host program in, for example, register address, buffer
fifo
- 一个先进先出的内存,使用一个同步时钟产生各种不同尺寸的高速缓冲-a first-in first out memory, uses a synchronising clock generics allow fifos of different sizes to be instantiated
accesschoujiang
- delphi写的抽奖程序,其中有些问题比方说数据同步提出了些个人的解决办法-delphi draw written procedures, for example, some of them made more data synchronization solution of individuals
procon
- 生产者消费者同步问题,用于模拟都线程的并行与互斥-Producer consumer synchronization, threads are used to simulate parallel and mutually exclusive
clk_en_gen
- 可靠的时钟产生器,采用同步设计,经过编译仿真,结果正确-Reliable clock generator, using synchronous design, compiled simulation, the results of the correct
divide6
- 采用同步设计的六分频电路,节省了系统的资源。编译仿真的结果正确-Synchronous design using the six-frequency circuits, saving system resources. Simulation results to compile correctly
tongbu1
- 使用全局变量同步线程的简单例子,是多核编程书上的一个例子,欢迎查看-The use of global variables of a simple example of thread synchronization, multi-core programming is an example of the book, please see
FIFO
- FIFO以及跨时钟域的同步问题。 FIFO有分离的地址总线和用以读写数据的数据通道,以及指示堆栈状态(满、将满等)的状态线。-FIFO as well as cross-clock domain synchronization. FIFO have separate address bus and read and write data to the data channel, as well as the instructions state stack (full, will be fu
JOREN
- 操作系统-进程同步之生产者和消费者 操作系统-进程同步之生产者和消费者-操作系统-进程同步之生产者和消费者
SystemOs
- 用多线程同步方法解决哲学家就餐问题 操作系统课程设计 Dining-Philosophers Problem-Dining-Philosophers Problem
OS
- 操作系统实验进程的描述与控制进程的同步与通信等实验源码-Descr iption of the experimental process of the operating system and control the process of synchronization and communication source, such as experimental
LED8
- 8灯渐变同步渐变P1=L1,L2,L3,L4,L5,L6,L7,L8-8LED
thread
- 这是学习操作系统时的作业,这个是关于线程同步的实验.内含有实验报告.-This is the time to learn the operation of the operating system, this is a thread synchronization on the experiment. The report contains experimental.
ParallelComputingwithMATLAB
- 用matlab 2007以上版本的并行计算工具箱和分布式计算引擎进行并行计算编程的示例代码,具有极高的参考价值,与user s guide同步-Matlab 2007 with the above version of the Parallel Computing Toolbox and Distributed Computing Programming parallel computing engine for the sample code has a very high reference
mune
- 线程同步机制。 互斥器的功能和临界区域很相似。区别是:Mutex所花费的时间比Critical Section多的多,但是Mutex是核心对象(Event、Semaphore也是),可以跨进程使用,而且等待一个被锁住的Mutex可以设定TIMEOUT,不会像Critical Section那样无法得知临界区域的情况,而一直死等。-Thread synchronization mechanism. Mutex' s function and the critical region is
Chapter1-5
- 第一章到第五章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例