搜索资源列表
AMBAaxi
- AMBA axi bus protocol: the documents for implementing AMBA axi
AXI_MIG
- ISE生成的AXI接口的MIG，内存控制器，语言：verilog-ISE generated the AXI interface MIG, memory controller, language: verilog
axi_slave
- AMBA axi利用verilog搭建的axi_slave模块-AMBA axi use verilog module built axi_slave
AXI_reference_guide
- 满足axi总线的读写操作，实现数据的高速传输，实现ps端与拍了端的通信-axi read and write operations