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rs-codec-8-4
- encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplic
ca_prng_latest.tar
- Pseudo random noise generator/ implemented in VHDL/Verilog
clk_gen
- this is a clock generator program by using concurrent language verilog hdl with xilinx ise.
sinwave-genertor
- sinwavw generator code in verilog this will helpful for generating a sinave without using a cordic
vftvdr
- 基于FPGA的DDS信号发生器设计，包含Quartus 的工程，打开即可使用，Verilog 语言编写！-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读 显示对应的拉丁字符的拼音 字典- 查看字典详细内容-FPGA design, including the Quartus project, open to use, Ve