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Verilog数字系统设计教程(第2版)
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed o
dlx_verilog.rar
- 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。,This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! T
nnARM_tb01_09_02
- arm processor verilog code
nnARM_tb01_07_19
- verilog code for ope processor
hmc-mips-7-3-15
- mips processor in verilog
fft
- vhdl code and verilog code for an 128 point fft processor which has to be executed in xlinx software as needed for course project
150110052-150110024-150110006
- central processor unit design in verilog
single_cpu_verilog
- 16位单周期处理器的verilog实现，简单易懂，对计算机的结构学习有帮助。-16 single-cycle processor verilog implement, easy to understand, the structure of learning computer help.