搜索资源列表
xilinx_timing_constains_training
- 很详细的讲解了关于xilinx时序约束的很多问题。-describe timing constains in xilinx FPGA design
license
- xilinx 13.1 that wrks with only
IF_SIG_CONTROL
- signal controls using IF for verilog. it modified Xilinx. it use just red, yellow and green signals.signal controls using IF for verilog. it modified Xilinx. it use just red, yellow and green signals.
MUTIPLIER_16
- 16位乘法器的工程，用xilinx ISE设计，供初学者学习-16 multiplier works, the ISE xilinx design, for beginners to learn
half_adder
- 一位半加器工程，用xilinx ISE设计，供初学者学习-A half adder project using xilinx the ISE design for beginners to learn
full_adder
- 一位全加器工程，用xilinx ISE设计，供初学者学习-A full adder works, the ISE design with xilinx for beginners to learn
counter_12
- 12进制计数器工程，用xilinx ISE设计，供初学者学习-12 hex counter project using xilinx the ISE design for beginners to learn
CLK_DIV
- 奇数倍和偶数倍分频器都包含在内，用xilinx ISE设计，供初学者学习-Odd times, and even multiple dividers are included in the ISE design with xilinx for beginners to learn
ise-10
- VHDL Xilinx ISE 10 Tutorial
9536
- Xilinx user constraints file for the cpld xc9536 or xc9536xl or xc9572 or xc9572xl
Xilinx
- 基于spartan V5的FPGA 分频器设计-Spartan V5 FPGA-based crossover design
fir-mat
- filtro pasabajos para hdl xilinx coeficientes positivos
ofdm_baseband_design_basedon_fpga
- 基于Xilinx FPGA的OFDM通信系统基带设计一书的源代码 -this is source code from a book
13.Anvyl_PmodAD1_Demo
- 用VHDL写的AD程序，使用与xilinx开发板。-Written using VHDL AD process, use and xilinx development board.
Xilinx_PCIe_BMD
- xilinx FPGA 开发 PCIe BMD DMA的verilog HDL源码-xilinx fpga pcie Gen 1/2 bus master device---PCIe DMA with verilog HDL
ug623Libraries-Guide-for-HDL-Designs
- Xilinx 官方 HDL 设计库指导，FPGA设计人员的好帮手-Xilinx HDL design library official guidance, FPGA designers a good helper
TechAss-2006
- un controller pi par le langage VHDL xilinx ise design 13.2
exp6_Uart
- xilinx FPGA的rs232 Verilog HDL程序-xilinx FPGA的rs232 Verilog HDL
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE
FFT8
- xilinx FFT complete code book can be designed with reference to the FFT