搜索资源列表
m_cycle_mips
- verilog设计的5状态多周期mips -multiple cycle mips CPU design of Verilog
Matrix
- Matrix manipulation in Assembly MIPS. Sum and Multiplication.
mult
- 用MIPS汇编语言实现32位机器正确计算出32位数的乘法- U7528M_ u6C47 u7F16 u8BED u8B00 u5B9E u73B032 u4F4D u673A u5668 u6B63 u786E u8BA1 u7B97 u51FA32 u4F4D u6570 u7684 u4E58 u6CD5
CPU
- 多周期CUP用MIPS汇编的实现，包含了测试指令。(Multi cycle CUP with MIPS compilation of the implementation, including the test instructions.)
MIPS1
- 可以计算一个表达式的值，支持sin,cos,tan,e,π Mars4.5编译通过(You can compute the value of an expression that supports sin, cos, Tan, e, PI, Mars4.5, compilation, and so on)
全排列汇编
- 读入整数，输出其全排列并按字典序输出，例如3会输出123,132,213,231,312,321。通过递归实现。(Read into the integer, output its full arrangement and output in the dictionary order)
lab
- 输入一个整数N，输出N到0的和，通过汇编语言编写(Enter an integer N, output N to 0, and write in assembly language)
os
- 基于mips的操作系统kernel文件的加载和镜像文件的创建(Kernel file loading and image file creation based on MIPS)