搜索资源列表
clock
- 用vhdl开发的up3 clock,可以在up3的led上显示24小时制时分秒
clock.rar
- VHDL编写的,实现电子手表功能,硬件语言描写,定时非常准确,VHDL prepared, electronic watches, functions, hardware descr iption languages, timing is very accurate
1234
- 多功能数字钟,、在quartus 2环境中编译通过; 4、仿真通过并得到正确的波形; 5、给出相应的设计报告 -Multifunction digital clock, in the quartus 2 compiler environment through 4, simulation through and get the correct waveform 5, gives the design report
clock
- EDA 数字钟实现文件 能够实现计时,闹钟,校时功能 -EDA digital clock time to achieve the realization of paper, alarm clock, school functions
any_div_freq
- 可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.-Can be arbitrary points on the input clock frequency (integer or decimal), with complete Quartus II project document.
clock
- 描述了24小时计时的数字钟,同时具有分秒计时的功能-Described a 24-hour digital time clock, at the same time every minute timer function
shizhong
- 简单的VB时钟控件操作,对于刚学习VB.net的人很有帮助-VB simple clock control operation, for people just learning VB.net helpful
workhard
- 数字钟 可实现正常计数校准 还有方电台报时功能 四低一高 闹钟功能-Digital clock can be calibrated to achieve a normal count timekeeping function of the radio side there are four low and one high alarm
clock
- 完成数字钟表的功能,可以实现整点报时,闹钟和设置时间-The completion of the functions of digital watches, you can bring the whole point timekeeping, alarm clock and set-up times
digital_clk
- 此程序是实现数字钟的,包括校时 闹钟 二十四小时和十二小时的转换-This procedure is to achieve digital clock, including the school alarm clock 24 hours and 12 hours the conversion
clock
- 电子课程设计数字钟的源代码,已在试验箱上实现,定义了管脚。可以调整时间-E-curriculum design digital clock source code has been achieved in the chamber, the definition of a pin. Can adjust the time
clk
- 通过一个主时钟信号完成异步FIFO读写时钟信号的产生。编译通过实现功能。-Through a master clock signal the completion of asynchronous FIFO read and write clock signal generation. Compiler through the implementation function.
clock
- 数字钟是采用数字电路实现“时”、“分”、“秒”数字显示的计时装置。由于数字集成电路的发展和石英晶体震荡器的使用,使得数字钟的精度、稳定度远远超过了机械钟表,已成为人们日常生活中必不可少的必需品。-Digital Clock is a digital circuit implementation, " when" , " sub" , " second" The figures show that the timing device. Digita
asynFifo
- 异步fifo在IC设计中,非常重要;是异步时钟域同步方法-Asynchronous fifo in IC design, is very important are asynchronous clock domain synchronization
EDAtest
- 关于数字钟的实现,用VHDL实现时,分,秒,的显示,并能报时-Digital clock on the realization of VHDL to achieve with hour, minute, seconds display, and time
clk_en_gen
- 可靠的时钟产生器,采用同步设计,经过编译仿真,结果正确-Reliable clock generator, using synchronous design, compiled simulation, the results of the correct
crc8
- 8bit CRC码生成器vhdl 代码,延时一个周期CRC码有效。-8bit crc code genergator,after delay one clock,crc code valid
clock
- 电子时钟简单设计模板,内含源代码,并可实现简单计时-Electronic Clock simple design template, containing the source code, and with a simple timing
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一,尽管在目前大部分设计中,广泛使用芯片厂家集成的锁相环资源,如altera 的PLL,Xilinx的DLL.来进行时钟的分频,倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
20080108103305384
- 本系统是采用EDA技术设计的一个简易的八音符电子琴和音乐发生器,该系统基于计算机中时钟分频器的原理,采用自顶向下的设计方法来实现,它可以通过按键输入来控制音响。系统由乐曲自动演奏模块、乐器演示模块琴/乐功能选择模块、音调发生模块和数控分频模块五个部分组成。系统实现是用硬件描述语言VHDL按模块化方式进行设计,然后进行编程、时序仿真、整合。本系统功能比较齐全,有一定的使用价值.-The system is designed using EDA technology with a simple ei