Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * M

卷积码维特比译码器设计输出完整电路进行误码率分析-Convolutional code Viterbi decoder integrated circuit design of the output bit error rate analysis

实现（2，1，6）卷积码的维比特译码源程序，采用了最大似然算法 介绍了软判决维特比译码算法过程的三个步骤：初始化，度量更新和回溯译码 -Achieve (2,1,6) convolutional code Viterbi decoder source code, using the maximum likelihood algorithm for soft decision Viterbi decoding algorithm process three steps: initiali

(2,1,5)的维特比译码器源码，能译码出经过编码后的卷积码-(2,1,5) Viterbi decoder source code, can decode the encoded convolutional code