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RS(255-233)decode
- 基于verilog HDL RS(255,223)的编译器源代码-Based on verilog HDL RS (255,223) of the compiler source code
control
- 用Verilog HDL 语言描述的自动转换量程频率计控制器-Automatic conversion range frequency meter controller described using Verilog HDL
lab4part5
- verilog HDL coding to display hexadecimal on FPGA
bin_count
- i m sending hdl code of dm using verilog and vhdl with all blocks contain fft,ifft,scrambler,transmitter,receiver.-i m sending hdl code of ofdm using verilog and vhdl with all blocks contain fft,ifft,scrambler,transmitter,receiver.
clk_gen
- this is a clock generator program by using concurrent language verilog hdl with xilinx ise.