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- 用VHDL语言编写的三位二进制的乘法器,其原理是每位相乘后再错位相加-using VHDL prepared by the three binary multipliers, the principle is that each subsequent dislocation multiplication sum
EP1C3_91_MULTI8X8
- 移位相加硬件乘法器设计 程序设计与硬件实验-Add hardware multiplier shift programming and hardware design experiment