Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * M

卷积码维特比译码器设计输出完整电路进行误码率分析-Convolutional code Viterbi decoder integrated circuit design of the output bit error rate analysis