搜索资源列表
fifo_ver_131
- fifo verilog hdl 源程序-fifo verilog hdl source
clock
- 用Verilog HDL写的数字时钟,已经在开发板上验证过的,绝对原创,使用数码管进行显示!
and_2
- 双输入与门的硬件描述语言。用verilog hdl描述。-Two-input AND gate hardware descr iption language。
manchester
- Verilog HDL 曼彻斯特编解码，16位并口的曼彻斯特编解码-manchester decode and encode Verilog
Xilinx_PCIe_BMD
- xilinx FPGA 开发 PCIe BMD DMA的verilog HDL源码-xilinx fpga pcie Gen 1/2 bus master device---PCIe DMA with verilog HDL
alu16
- 16位运算器，用实例化模块链接，是采用Verilog hdl编程，是实现fpga的代码-16-bit arithmetic unit, with links to instantiate module is using Verilog hdl programming, is to achieve the fpga code
sn74181
- 4位运算器采用sn74181，是采用Verilog hdl编程，是实现fpga的代码，实现了其模块的48种功能，-4 operator uses sn74181, is the use of Verilog hdl programming, is to achieve the fpga code, achieved its module 48 kinds of functions,
exp6_Uart
- xilinx FPGA的rs232 Verilog HDL程序-xilinx FPGA的rs232 Verilog HDL
frequence
- verilog hdl语言编写，频率测量系统中的一个子单元-verilog hdl Language, frequency measurement system in a sub-unit
Adder_12bit
- 带进位的12位宽超前进位加法器，可以在工程中直接调用。使用Verilog HDL编写。-A 12-bit wide carry lookahead adder with carry bit, that can be called directly in the project. Written using Verilog HDL.