verilog hdl语言编写，频率测量系统中的一个子单元-verilog hdl Language, frequency measurement system in a sub-unit

带进位的12位宽超前进位加法器，可以在工程中直接调用。使用Verilog HDL编写。-A 12-bit wide carry lookahead adder with carry bit, that can be called directly in the project. Written using Verilog HDL.