搜索资源列表
Multiplier
- 乘法器课程报告，华莱士树算法硬件实现，讲解详细-Multiplier course reports, Wallace tree algorithm implemented in hardware
verific_evaluation
- 这是一个比较大的数字逻辑电路的verilog代码，具有版权保护，可以实现多输入乘法器。-This is a relatively large verilog code digital logic circuits, with copyright protection, you can achieve multiple-input multiplier.
FPGA-Implementation
- 20×18位符号定点乘法器的FPGA实现-2018 fixed-point multiplier symbol FPGA Implementation
booth_multiply
- 布斯乘法器，采用verilog语言实现 经过modelsim仿真-Booth multiplier using verilog language through modelsim simulation
Wallace-chengfaqi
- 对wallace tree的学的代码 大家对乘法器有的认识 对学习帮助很大-Wallace tree learning a 8 bit multiplier is very good code
some-kinds-multiple-Verilog
- 几种常见的乘法器的verilog代码，已经试过可用-some kinds of multiplier for verilog, it is useful
DDC-based-on-CORDIC-.pdf
- FPGA平台上基于CORDIC架构实现DDC的方案，将传统的本振和混频两个单元合在一起完成，省去了查找表和硬件乘法器资源-Implementation of DDC CORDIC architecture scheme based on the FPGA platform, the traditional local oscillator and mixer two units together to complete, eliminating the look-up table and har
multer
- 16*16位的乘法器，用booth编码，采用Wallace树结构，用超前进位加法器。-booth encoded multiplier
adder_sub_mul
- 加法器，减法器，乘法器，超前进位，一位拓展成四位-adder and subber are written by the language of VerilogHDL one bit to four bits.