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Mini_Proj3
- Embedded 16 bit adder designed and implemented on Altera FPGA DE1 board using SOPC system builder and tested with NIO2 software. Language:Verilog and C
16-leading-adder-Verilog-program
- 这是一个16位超前进位加法器的Verilog程序。-This is a 16 bit leading adder verilog program.
Vhdl-Implementation-of--Fast-32x32-Multiplier-Bas
- The Vedic mathematics is quite different from conventional method of multiplication like adder and shifter. This mathematics is mainly based on sixteen principles. The multiplier (referred henceforth as Vedic multiplier) architecture base
16-bit-adders
- 16 bit ripple carry adder. also called as carry propagate ader
mips.tar
- VERILOG CODE FOR 16- bit ripple carry adder
184081165-16-Bit-Wave-Pipelined-Sparse-Tree-RSFQ-
- In this system, we discuss the architecture, design, and testing of the first 16-bit asynchronous wave-pipelined sparse-tree superconductor rapid single flux quantum adder implemented using the ISTEC 10 kA/cm 2ADP2.1 fabrication process. Compar
16位流水线加法器
- 16位流水线加法器报告，内涵主代码测试代码测试结果及分析(16 bit pipelined adder)