8位全加器的VHDL语言描述，有需要的顶一下。-8-bit full adder described in the VHDL language, there is a need to click the top.

1位全加器 可以进行1位的二进制码的加法 想进行改进 改为4位或8位的全加器代码-A full adder can be an addition of the binary code would be changed to improve the 4 or 8-bit full adder code