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TCPIP协议栈的设计与实现 焦海波
- LwIP是TCP/IP协议栈的一个实现。它的目的是减少内存使用率和代码大小，使LwIP适用于资源受限系统比如嵌入式系统。为了减少处理和内存需求，LwIP使用不需要任何数据复制的经过裁剪的API。 本文描述了LwIP的设计与实现。描述了在协议栈实现中以及像内存与缓冲管理这样的子系统中使用的算法和数据结构。本文还包括LwIP的参考手册以及使用LwIP的代码例子。(LwIP is an implementation of the TCP/IP protocol stack. Its purpose
U-Boot启动第二阶段代码分析
- U-Boot第一阶段的启动流程。(nandflash启动，把nand的4k代码考到sram中，因为nand没址线，不能映射到内存，所以通过sram进行过度，sram中4k代码把整个uboot拷贝到sdram上，初始化好堆栈，为c语言提供条件，进入uboot的第二阶段！ )这个阶段主要是初始化硬件设备，为加载U-Boot的第二阶段代码准备RAM空间最后跳转到lib_arm/board.c中start_armboot函数，这是第二阶段的入口点。(U-Boot first phase of the s
STM32F4xx中文参考手册
- 提供有关使用 STM32F405xx/07xx、 STM32F415xx/17xx、STM32F42xxx 和 STM32F43xxx 微控制器存储器与外设的完整信息(Provide complete information about the use of STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx, and STM32F43xxx microcontroller memory and peripherals)
STM32F10xxx参考手册中文版
- 提供关于如何使用小容量、中容量和大容量的STM32F101xx、STM32F102xx或者STM32F103xx微控制器的存储器和外设的详细信息(Provide detailed information about how to use small capacity, medium capacity and large capacity STM32F101xx, STM32F102xx or STM32F103xx microcontroller's memory and peripherals
决策树+神经网络
- 人工智能AI，决策树和神经网络的原理说明(MEMORY-EFFICIENT GLOBAL REFINEMENT OF DECISION-TREE ENSEMBLES AND ITS APPLICATION TO FACE ALIGNMENT)
Bidirectional LSTM-CRF Models for Sequence Tagging
- In this paper, we propose a variety of Long Short-Term Memory (LSTM) based models for sequence tagging. These models include LSTM networks, bidirectional LSTM (BI-LSTM) networks, LSTM with a Conditional Random Field (CRF) layer (LSTM-CRF) and bidirec
AT24C01A_Datasheet
- The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many automoti
C和指针课后习题答案
- 本书书写了C和指针的课后习题答案，供大家参考。 Pointers On C Instructor’s Guide Chapter 1 A Quick Start Chapter 2 Basic Concepts Chapter 3 Data Chapter 4 Statements Chapter 5 Operators and Expressions Chapter 6 Pointers Chapter 7 Functions Chapter 8 Arrays
DDR4 SODIMM标准
- This specification defines the electrical and mechanical requirements for 260 pin, 1.2 V (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SO-DIMMs). These DDR4 SO-DIMMs are intended for use as main me