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verilog
- 讲述的是verilog HDL 的一些实际应用与联系。还宝库奥一些总结性的知识。-About the verilog HDL and contact some of the practical application. Treasure-house of Austria is also a number of conclusive knowledge.
i2c.tar
- i2c core for verilog hdl
i2c_customer_pack
- i2c core for verilog hdl
VerilogHDL_tuxiang
- 介绍一种用于卫星姿态测量的CMOS图像敏感器--STAR250的时序驱动信号,并使用Verilog HDL语言设计驱动时序电路。经布线、仿真、测试后验证了驱动信号的正确性。 -Introduce a measurement for the satellite attitude CMOS image sensor- STAR250 timing drive signals, and use the Verilog HDL language design-driven sequential circ
FPGAdeguangshanjiancejishu
- 本文档设计了1光栅位移传感器信号的接收、光栅位移传感器信号的整形及电平转换电路设计,用Verilog HDL描述了锁相倍频细分和零位信号处理电路。利用FPGA实现光栅位移系统与上位机接口的电路原理框图-This document designed a grating displacement sensor signal reception, grating displacement sensor signal shaping and level conversion circuit design
Verilog_shuzisheji
- 本章的目的是想通过对数字信号处理、计算(Computing)、算法和数据结构、编程语言和 程序、体系结构和硬线逻辑等基本概念的介绍,了解算法与硬线逻辑之间的关系从而引入 利用Verilog HDL 硬件描述语言设计复杂的数字逻辑系统的概念和方法。向读者展示一种 九十年代才真正开始在美国等先进的工业国家逐步推广的数字逻辑系统的设计方法-Purpose of this chapter is to through digital signal processing, computing (
Verilog-HDL-standard
- VERILOG的编码设计规范,使你的程序容易被理解,阅读和维护-VERILOG coding design specifications, to make your program easier to understand, read and maintain
verilog-coding-rules
- Verilog HDL可综合RTL级代码设计规范及风格-Verilog HDL RTL level code design specifications and style
A-Verilog-HDL-Test-Bench-Primer
- 学习资料:详细说明了如何用Verilog语言编写Testbench文件-Learning materials: detailed descr iption of how to use Verilog language Testbench file
Verilog-CAN-controler
- verilog hdl 语 言 实 现 的 CAN 控 制 器-CAN controller verilog hdl language
Verilog-HDL
- 重点介绍verilog VHL语言结构及使用方法-Highlights verilog VHL language structure and use
lab-1-ALU-design-with-Verilog-HDL
- cpu设计的运算器部分verilog代码,实验资料,包括原理和代码,在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
verilog-uart
- UART(Universal Asynchronous Receiver Transmitter,通用异步收发器)是广泛使用的异步串行数据通信协议。下面首先介绍UART硬件接口及电平转换电路,分析UART的传输时序并利用Verilog HDL语言进行建模与仿真,最后通过开发板与PC相连进行RS-232通信来测试UART收发器的正确性。-UART (Universal Asynchronous Receiver Transmitter, Universal Asynchronous Receive
Verilog-HDL
- 给出了学习verilog心得,其中包含了典型的代码例子,适合初学入门。-verilog program demo and method.
基于VERILOG HDL的建议电子琴
- 7个按键控制1234567个音,3首内置乐曲,按键可播放,可切换
Freescale-Verilog-HDL-Coding
- 飞思卡尔verilog语言编程规范文件,很有借鉴意义-Freescale verilog programming language specification file,Great reference
verilog-ieee
- The Verilog ¤ Hardware Descr iption Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it
Verilog-HDL-Code-Examples
- various verilog code ezamples for brginners.good point to start with.
Verilog--exzampie
- Verilog的大量代码,拿去好好学习吧-verilog hdl exzamples
Verilog-DATAS-xiayuwen
- 3.1 引言 3.2 Verilog HDL基本结构 3.3 数据类型及常量、变量 3.4 运算符及表达式 3.5 语句 3.6 赋值语句和块语句 3.7 条件语句3.8 循环语句 3.9 结构说明语句 3.10 编译预处理语句 3.11 语句的顺序执行与并行执行 3.12 不同抽象级别的Verilog HDL模型 3.13 设计技巧-3.1 Introduction 3.2 Verilog HDL basic structure 3.3