搜索资源列表
module-sj001
- 这是基于fpga设计的数字频率计每个模块的 verilog hdl-This is based on verilog hdl fpga design of digital frequency meter for each module
18.uart
- 用Verilog HDL编写的uart程序，亲测可行，注释很详细！-Written using Verilog HDL uart program, pro-test is feasible, very detailed notes!
interleaver
- 移动通信中信道编码交织器的 Verilog hdl 实现-Verilog hdl mobile communication channel coding interleaver implementations
turbo_encode
- 移动通信技术中信道编码的并串转换的Verilog hdl 实现-Channel coding of mobile communication technology and the string conversion of Verilog hdl realization
ldpc
- 移动通信技术中信道编码的LDPC码的Verilog hdl 实现-Verilog hdl channel coding of mobile communication technology to achieve LDPC codes
MS_LDPC
- 移动通信技术中信道编码的LDPC码的译码Verilog hdl 实现-Decoding Verilog hdl channel coding of mobile communication technology to achieve LDPC codes
vnp
- 移动通信技术中信道编码的LDPC码的VNP的Verilog hdl 实现-Channel coding of mobile communication technology LDPC code VNP realization of Verilog hdl
FPGA_PID
- 本文讲的是基于FPGA的模糊PID控制器实现,详细介绍了Verilog HDL怎样用FPGA实现PID控制器-This article tells of fuzzy PID controller based on FPGA implementation details of how to use FPGA Verilog HDL realize the PID controller
count_1000
- 适用于verilog hdl初学者——0-999加法计数器，内带vwf波形仿真-Suitable for beginners 0-999 adding counter verilog hdl, which with vwf waveform simulation
hardwired
- 掌握硬连线控制器的设计方法。掌握硬连线控制器的Verilog HDL描述方法。了解QUARTUS II硬件描述语言和原理图混合输入设计的过程。 -Master the design method of hard wired controller. Grasp the hard wired controller Verilog HDL descr iption method. To understand the process of QUARTUS II hardware descr ipti
_Verilog_HDL-study
- 对Verilog hdl语法学习有较大帮助 适合新手学习-Learning grammar for Verilog hdl great help for novices to learn
uart
- 基于Verilog HDL设计的UART
LAB3_HDL
- Code Verilog HDL LAB 3 UIT
notes_Lecture-1
- Advanced Digital Design with Verilog HDL Lecture 1
notes_Lecture-3-4
- Advance Design With Verilog HDL Lecture 3 & 4
CProgrammingforabsolutebeginners_WeLearnFree
- ebook verilog HDL programming book
scan-led
- 7段共阳极数码管，译码显示，Verilog HDL程序-Code based on Verilog HDL
key_debounce
- 按键去抖动，Verilog HDL语言，比较按键去抖和不去抖的区别
shizhong
- 基于Verilog HDL语言的数字时钟程序，有秒脉冲，，计数，译码显示等部分-based on Verilog HDL language,about clock
FPGA-Prototyping-By-Verilog-Examples
- HDL (hardware descr iption language) and FPGA (field-programmable gate array) devices allow designers to quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify operation of the physical impl