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phase_test
- 基于verilog的鉴相器设计，鉴相器是锁相环的一部分，功能是检测两个时钟是否同步-The phase detector based on verilog design, PLL phase detector is part of function is to test whether the two clock synchronization
DVB
- 通过分析8PSK 调制方式的载波恢复、定时恢复算法, 提出了一种适用于新一代数字卫星电视标准DVB S2 的全数字解调算法, 改进了相位频率检测( PFD) 算法以适合于8PSK 解调. 载波恢复采用频率检测( FD) 和相位频率 检测相结合的结构, 跟踪范围超过1 倍符号率. 采用Gardner TED 算法进行定时恢复.-By analyzing the 8PSK modulation carrier recovery, timing recovery algori
111
- 数字鉴相器,数字锁相环频率合成系统FPGA的实现,很有借鉴价值-Digital phase detector, digital PLL frequency synthesizer system FPGA realization of referential value
si4133-datasheet
- 该Si4133是一个单片集成电路，既执行IF和双频 RF合成为无线通信应用。在Si4133 包括三个和VCO，环路滤波器，参考和VCO分频器，相位 探测器。除法和可编程掉电设置与threewire 串行接口。-The Si4133 is a monolithic integrated circuit, both the implementation of the IF and dual-band RF synthesis for wireless comm
MultiFunctionCounter
- 此为我们组在学校比赛中设计的多功能计数器的系统设计文档，此多功能计数器即是测频测相器（硬件使用EPM240采样和计数，mega16取数和控制）-This is our group s multi-purpose counter system design documents in school competitions. This multi-function counter that is the frequency and phase detector(hardware using EPM2
DuogongnenJiishuqi
- 此为我们组在学校比赛中设计的多功能计数器的系统设计文档，此多功能计数器即是测频测相器（硬件使用EPM240采样和计数，mega16取数和控制）-This is our group s multi-purpose counter system design documents in school competitions. This multi-function counter that is the frequency and phase detector(hardware using EPM2
RLSxiebojiance
- 以自适应线性组合器为时变谐波检测器的模型, 根据逆归最小乘自适应滤波算法较好的跟踪性能, 使之应用于时变谐波的跟踪检测。仿真表明该方法比以往的基于最小均方 自适应滤波算法的谐波幅值和相位参数的测定具有更好的跟踪效果。-Adaptive linear combiner with harmonic detector is too variable model, according to inverse normalized least square adaptive filter algorit
ppl
- 锁相电路是相位锁定环(Phase Locked Loop)的简称，主要由鉴相器、环路滤波、压控振荡器成 。主要是要掌握LabVIEW图形化编程特点，-PLL circuit is phase-locked loop (Phase Locked Loop) for short, mainly by the phase detector, loop filter, VCO into. Mainly to grasp the features of LabVIEW graphical programm
DPLL
- 数字锁相环频率合成器的设计,鉴相器、环路滤波器、数控振荡器、反馈分频器-Digital PLL frequency synthesizer, phase detector, loop filter, NCO, feedback divider
Phase-and-Frequency-Detector
- 针对锁频锁相器( Phase and Frequency Detector, PFD) 应用于低信噪比、大频偏的条件, 通过理论分析和仿真验证阐述了窗口类型对系统频偏捕获速度、范围、噪声门限及相位噪声抖动的影响机理. 推导出等效相位噪声功率谱密度的表达式. 证明了大窗口具有更低的噪声门限和更小的稳态相位抖动, 但捕获速度较慢. 为了提高捕获速度, 对鉴相器输出值取极性运算得到改进的PFD 算法. 新算法不仅能增加鉴相增益提高捕获速度 还可以减少等效噪声功率谱密度降低相位抖动 同时新算法不需要乘法
gardnertimingdetector
- This paper presents the simulation performance of the all-digital symbol timing recovery using the Gardner Timing Error Detector over π/4-DQPSK modulation. The open loop statistics, the S-curve and the normalized timing error variance, were investiga
multiscale
- 按照二维函数的特点和视觉机制,提出了用来捕捉纹理基元的纹理检测器函数,基于纹理检测器和扩展的小波变换,提出了基于能量分解的影像纹理多尺度分析方法,并按照神经动力学的侧抑制和端点抑制等理论,实现了对多尺度纹理特征的融合，这一多尺度分析方法直接将影像纹理能量在时间一尺度空间分解,包含了相位信息,避免了基于线性变换多尺度分解引起的能量与相位分离,为纹理分析提供了一个层次性的框架,有效提高了纹理的识别能力。-According to the characteristics of two-dimensio
phase-detector-PLL-demo
- 要用phase detector，可到现在还不知道PLL是什么东东，不知道phase detector是如何实现的。 可叹自己没有把事物的因果分析清楚，可叹国外的人懂的比自己多。感谢国外作者的分享。-phase detector PLL demo
encoder
- 两相编码器应用程序,公制英制数据输出,在一种视频检测仪上使用-The two-phase encoder application, metricinch data output,Use on a video detector
pll
- A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. While there are several differing types, it is easy to initially visualize as an electronic circu