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xuliejiance
- 《序列检测器》绝对好用的EDA实验程序,已经通过测试！VHDL语言编写-"Sequence Detector" absolutely good for EDA experimental procedure, he has passed the test! VHDL language
VHDL设计的相关实验，包括4位可逆计数器
- VHDL设计的相关实验，包括4位可逆计数器，4位可逆二进制代码－格雷码转换器设计、序列检测器的设计、基于ROM的正弦波发生器的设计、数字密码锁的设计与实现。-VHDL design of experiments, including four reversible counters, four reversible binary code- Gray code converter design, the sequence detector design, the ROM-based sine w
EDA
- 60进制计数器 序列检测器 适用于MAX PLUS2程序开发-60 hexadecimal counter sequence detector for MAX PLUS2 development
111
- 使用JK触发器设计111序列检测器，当检测到输入为111时输出为1，否则为0-JK flip-flop design using the sequence detector 111, when input 111 is detected when the output 1, otherwise 0
state
- 实现的是序列检测器，给出输入序列，并进行检验，如果满足连续为110011101则输出为1-To achieve the sequence detector, given the input sequence, and tested, if the continuous output of 1 to 110,011,101
main-dc
- New Positive sequence Voltage Detector for Grid Synchronization of Power Converters under Faulty Grid Conditions
01712059
- New Positive-sequence Voltage Detector for Grid Synchronization of Power Converters under Faulty Grid Conditions
detector
- vhdl语言写的状态机，完成序列检测的功能，包含代码和仿真图-VHDL language used to write the state machine, complete sequence detection features, including code and simulation Figure
A-Verilog-Model-of-Universal-Sequence-Detector.ra
- a verilog model of universal seq detector
exp4_fpga_
- finite state machine consist of sequence detector and traffice light controller and vending machine
renmin331
- FPJA Verilog序列检测器1001 -1001 Sequence Detector
xuliejiance
- 设计一个二值序列检测器，即如果连续检测到1110010序列就输出为1，否则为0。-Design of a binary sequence detector, i.e., if the sequence is continuously detected 1110010 outputs 1, otherwise 0.
eight-number
- 八位数据选择器和序列10010检测器，数据选择器具有数据选择功能，序列检测器是一个自动检测序列功能-Eight data selector 10010 and the sequence detector, a data selector having a data selection function, the sequence detector is a sequence of automatic detection function
VHDL-sequence-detector
- VHDL 序列检测 对特定的序列进行检测-VHDL sequence detector