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verilog基本功
- verilog基本功---详细介绍verilog编码的基本规则，深入的讲解了一些难点和重点，非常适合初学者学习
Verilog
- 是摩托罗拉关于Verilog HDL的开发规范，相信对于学习Verilog程序设计的人会有很大的帮助-Motorola on the development of Verilog HDL specification, I believe that learning Verilog for programming will be of great help to people
IEEE_Verilog_2001
- Verilog 2001 编程规范，作为ASIC和FPGA逻辑开发人员学习不可多得的资料，也可以作为逻辑开发高手们学习查阅的工具。新手们可以按照实例自己编程操练。
Code
- DSP学习板上的例子程序包括 AD转换 CAN总线 SPI SCI -Examples of on-board DSP learning process includes the AD conversion CAN Bus SPI SCI
verilog
- 这是初步学习verilog的有用资料．包括了全部的基础知识．有需要的朋友赶快来下载哦．-This is a preliminary study useful information verilog. Including all the basic knowledge. There is a need to get friends to download Oh.
Verilog
- Verilog语言学习资料，希望对给为有一点帮助哈-Verilog language learning materials, hoping to have some help on to Kazakhstan
eda-verilog-report
- EDA的实验报告，有六个入门级实验，写得比较详细，方便大家学习，传阅-EDA lab reports, there are six entry-level experiment, written in more detail, to facilitate learning, circulated
verilog
- 这是一款学习板的基础实验代码，对于FPGA学习有很好的指导作用。-This is a learning board is based on experimental code, good for the FPGA learning guide。
Verilog
- verilog学习书籍，很容易上手 希望大家能够喜欢-verilog study book，it is easy to study, hope who will happy
A-Verilog-HDL-Test-Bench-Primer
- 学习资料：详细说明了如何用Verilog语言编写Testbench文件-Learning materials: detailed descr iption of how to use Verilog language Testbench file
learnVerilogHDL
- Verilog 学习资料，有例子和实际操作过程，适合初学者-Verilog learning materials, there are examples and actual operation process, suitable for beginners
Verilog-HDL
- 给出了学习verilog心得，其中包含了典型的代码例子，适合初学入门。-verilog program demo and method.
How-to-leanr-verilog
- Verilog 程序的学习，Verilog是通信工程专业学生经常使用的一种仿真程序-Verilog program of study, Verilog is a simulation program communication engineering students often use
Verilog
- 夏宇闻数字逻辑设计，非常好的VHDL学习资料，不多说了-Xia Wen digital logic design, VHDL very good learning materials, not much to say
verilog
- verilog 学习入门 非常适合初学者 讲解非常详细-verilog 学习入门 非常适合初学者 讲解非常详细
verilog
- verilog语言入门,可以帮助新手学习verilog语言，即VHDL-verilog Language portal that can help novices learn verilog language, VHDL
verilog-hdl(VIA-COMPANY-DOCUMENTS)
- verilog hdl学习 威盛内部资料-verilog hdl language(VIA reference document)
Verilog--exzampie
- Verilog的大量代码，拿去好好学习吧-verilog hdl exzamples
14_ethernet_test
- 千兆网学习代码 ISE，状态机实现数据打包，基于PHY芯片实现数据传输(ethernet communication sample with verilog,state machine)
《HELLO FPGA》-Verilog的关键问题解惑
- 《HELLO FPGA》-Verilog的关键问题解惑,解决Verilog学习过程中的一些问题。