搜索资源列表
DDDC
- 采用FPGA中的Verilog编程语言实现无线通信中数字上变频的功能-Using the FPGA Verilog programming language on the conversion of digital wireless communication function
IEEE_Verilog_2001
- Verilog 2001 编程规范，作为ASIC和FPGA逻辑开发人员学习不可多得的资料，也可以作为逻辑开发高手们学习查阅的工具。新手们可以按照实例自己编程操练。
DDS
- 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
dds
- 基于FPGA的双路可移相任意波形发生器 Altera中国大学生电子设计文章竞赛获奖作品刊登-FPGA-based dual phase shifter can be arbitrary waveform generator Altera China Undergraduate Electronic Design Contest winning entries published articles
FPGA_based_infrared_receiver_module
- 基于FPGA的红外接收模块，内含代码，采用VERILOG编写。-FPGA-based infrared receiver module, containing the code prepared by the use of Verilog.
FPGAFIR
- FPGA-based high-order FIR filter design
FPGA_8051core
- FPGA中嵌入8051单片机核的具体操作方法，有图示说明。-8051 single-chip FPGA embedded in the concrete operation of nuclear, there are icons that.
xapp341
- verilog uart for spartan 3 fpga, its great
DDCFPGA
- 针对DVB-T标准ETSI EN 300 744 V1.5.1,设计了可用于DVB-T接收整机的多速率DDC模块,并在FPGA中仿真实现.在复用数字振荡混频模块的基础上,根据输入信号的不同带宽(6M/8MHz)选择不同的抽取滤波器组完成抽取因子为3或4的多速率处理任务,利用两级半带滤波器(HBF)级联完成4倍抽取滤波,单级奈奎斯特滤波器完成3倍抽取滤波.-For the DVB-T standard ETSI EN 300 744 V1.5.1, designed for DVB-T recei
median
- 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1,
sobel_filter
- implementation of SOBEL filter using FPGA board RC200 in handle-c
gaijinjuzhenqiuniFPGA
- 改进的矩阵求逆的FPGA设计和实现（文章）感觉写得很不错-Improved matrix inversion of the FPGA design and implementation (article) wrote very good feeling
8254Verilog
- 用Verilog语言编写程序，基于FPGA实现设计8254的相关电子文件-With the Verilog programming language, based on FPGA to achieve the relevant electronic document design 8254
DDRcontroller
- 对DDR控制器的FPGA实现及其代码和参考注释-verilog source code written to read and write DDR
基于FPGA的巴克码发生器与识别器的设计
- 详细介绍了7位巴克码以及帧同步，7位巴克码与帧同步的关系。-Details of the seven Barker code and frame synchronization, 7 Barker code and frame synchronization relationship.
ddc
- 电子科大2009-应用于无线电监测的高速信号处理平台设计，软件无线电的DDC的FPGA实现！-UESTC 2009- applies to wireless monitoring of high-speed signal processing platform design, software radio DDC' s FPGA implementation!
FPGAdeguangshanjiancejishu
- 本文档设计了1光栅位移传感器信号的接收、光栅位移传感器信号的整形及电平转换电路设计，用Verilog HDL描述了锁相倍频细分和零位信号处理电路。利用FPGA实现光栅位移系统与上位机接口的电路原理框图-This document designed a grating displacement sensor signal reception, grating displacement sensor signal shaping and level conversion circuit design
verilog
- 这是一款学习板的基础实验代码，对于FPGA学习有很好的指导作用。-This is a learning board is based on experimental code, good for the FPGA learning guide。
FPGA--uart(verilog)
- verilog uart 源码，编译器ISE9.1i版本，很有用的源码-verilog uart code
fpga-verilog
- 基于fpga-verilog的音频设计，实现音频功能-the fpga-verilog Audio Design