搜索资源列表
VERILOGUSB2.0-IP
- USB IP核 verilog 语言 完整的use ip核-use ip verilog HDL
april2010_1
- 基于FPGA的方向滤波指纹图像增强算法实现，本文利用FPGA具有丰富寄存器资源、可满足高速系统设计等特点，设计了一种基于FPGA纯硬件方式实现方向滤波的指纹图像增强算法。设计采用寄存器传输级（RTL）硬件描述语言（Verilog HDL），利用时分复用和流水线处理等技术，完成了方向滤波指纹图像增强算法在FPGA上的实现。-Directional filtering fingerprint image enhancement algorithm based on FPGA using the FP
Quartus_II
- Quartus_II官方教程-中文版,适合VHDL及VERILOG HDL语言学习者使用-Quartus_II the Official tutorial- Chinese version for VHDL and VERILOG HDL language learners
verilogPHDL
- verilog+HDL经典教程 很详细的编程资料，而且浅显易懂-verilog+HDL classic very detailed tutorial programming information, and easy to understand
Handboook-Bucknell
- Handbook on verilog HDL
veriloghdl
- verilog HDL 实用教程 包含基础的概念和一些简单应用实例-the verilog HDL practical tutorial contains the concept and some simple application examples
vedicmuliplier
- Vedic multiplier design in Verilog HDL
ripple-carry-array-mult
- Ripple carry array multiplier design in verilog HDL
carrysave-array-mult
- Carry save array multiplier design in verilog HDL
verilogHDL
- 夏雨闻经典Verilog HDL详介绍了verilog HDL语法规范和无数经典例程，是和初学者学习，简单易懂。-Xia Yu Wen the classic Verilog HDL detailed introduction verilog HDL syntax specification and countless classic routines, and for beginners to learn, easy to understand.
High-speed-Digital-Design
- 高速数字设计，针对verilog HDL，中文版-High-speed digital design verilog HDL, the Chinese version
fpga-draw
- 二维图形加速器设计与实现。采用Verilog HDL语言对各功能模块进行了设计,包括画线、画圆、画椭圆、多边形填充以及区域复制等,总结了一套将算法使用硬件描述语言实现的一般流程.这是本人花了50大洋买的，吐血奉献-Design and implementation of a two-dimensional graphics accelerator. Using Verilog HDL language of each functional module design, draw lines, d
fpga
- 这是一个利用verilog HDL语言编写的自动频率计设计项目，能运行-This is a verilog HDL language automatic frequency meter design projects, and be able to run
Verilogpinlvji
- 基于verilog HDL的频率计设计，多个模块，误差较小。-Based on the the verilog HDL frequency meter design, multiple modules, the error is smaller.
lab-4-cpu-design-with-Verilog-HDL
- 用veriloghdl 编写的cpu代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-CPU code, written in veriloghdl modusim simulation through, including the principle diagram and code, in the form of a lab report write
rmii
- rmii 以太网接口时序源代码，值得开发借鉴的哦-verilog hdl
ht_fifo
- fifo 读写代码，能够进行速率匹配，很好的源代码-verilog hdl
crc32
- crc-32 主要用于网络传输中的 检测，防止错误数据传输-verilog hdl
MOTOROLA-Verilog-HDL-Coding-standard
- 文档是关于verilogHDL的代码规范的，编写方是MOTOROLA，对于规范VerilogHDL格式有借鉴意义-Document is about verilogHDL code specification, the preparation side is MOTOROLA, VerilogHDL format for standardizing reference
src
- Concatenator for calculator synthesizable in verilog hdl.-Concatenator for calculator synthesizable in verilog hdl.