搜索资源列表
Fibona
- 基于汇编和MIPS的基础,完成对斐波纳挈数列的产生过程,十分适合于初学者进行学习-Compilation and MIPS-based foundation, the completion of Fei Bona pull out series production process, very suitable for beginners to learn
MIPS_EJTAG.doc
- MIPS JTAG介绍文档,比较少人用MIPS,这是用龙芯时找到的资料-MIPS JTAG introduced the document, relatively few people use MIPS, which is used to find information when Godson
ca01
- The Computer Architecture Lecture Notes. It includes general information about CPU and MIPS. Also, It mentions about RISC and CISC microprocessor.
IDT-MIPS-R3000
- IDT R30xx Family Software Reference Manual This manual is targeted to a systems programmer building an R30xx based system. It contains the architecture specific operations and programming conventions relevant to such a programmer.
ChapterP2
- basic information about MIPS architecture
mips_file
- mips files uploaded full verilog sourse code
mips.tar
- VERILOG CODE FOR 16- bit ripple carry adder
MIPS-architecture-vol-IIa.pdf
- MIPS32 Architecture Volume II pdf
pipelined-mips-cpu-master
- misp 5 stage pipeline
mips_pipelined2
- verilog code for mips
Three-phase-smart-meter-design
- 充分地利用了DSP强大的信号处理能力和现代数值分析方法。 设计了电能表前端采样及计量模块的硬件,以及一套符合国标GB/T 17883-1999的 0.2S 级精度要求的算法,同时扩展了谐波分析功能。系统概述为:三相电压、电流 AD 采样,采样数据通过串口送至处理器(DSP),由 DSP 对采样数据作电参数计 量和谐波分析,处理结果通过定制 LCD 显示,并通过脉冲口发出有功、无功校 表脉冲。DSP 采用 ADI 公司的 BLACKFIN531-16 位定点芯片,最高处理能力可
Pipeline5
- Introduction to design MIPS-pipeline processor
capture2
- H264图像捕捉功能源代码,适用于嵌入式开发,兼容UVC,已经在mips平台测试OK-H264 image capture function source code, suitable for embedded development, compatible with UVC, has been tested in the MIPs platform OK
MD01024-2B-P5600-DTS-01.00.pdf
- MIPS P5600 Datasheet
RE4B-EN
- Reverse Engineering for Beginners by Dennis Yurichev
单周期处理器设计基础
- 基于MIPS指令集的单周期处理器设计课件,可以使用verilog语言实现。