搜索资源列表
DDS
- 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
fre_ctrl
- 利用verilog语言，从上至下层次管理的设计思想；Verilog HDL的行为描述和结构描述,实现8位频率计，4个0检测修正电路的原理说明-The use of Verilog language, top-down hierarchical management design idea Verilog HDL descr iption of the behavior and structure of a descr iption of the realization of frequency
dds
- 自己收集的一些关于DDS的文章，主要讲述了DDS原理以及如何利用verilog实现DDS-To collect some of their articles on the DDS, the main principle on the DDS and how to use DDS to achieve verilog
DDCFPGA
- 针对DVB-T标准ETSI EN 300 744 V1.5.1,设计了可用于DVB-T接收整机的多速率DDC模块,并在FPGA中仿真实现.在复用数字振荡混频模块的基础上,根据输入信号的不同带宽(6M/8MHz)选择不同的抽取滤波器组完成抽取因子为3或4的多速率处理任务,利用两级半带滤波器(HBF)级联完成4倍抽取滤波,单级奈奎斯特滤波器完成3倍抽取滤波.-For the DVB-T standard ETSI EN 300 744 V1.5.1, designed for DVB-T recei
median
- 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1,
gaijinjuzhenqiuniFPGA
- 改进的矩阵求逆的FPGA设计和实现（文章）感觉写得很不错-Improved matrix inversion of the FPGA design and implementation (article) wrote very good feeling
8254Verilog
- 用Verilog语言编写程序，基于FPGA实现设计8254的相关电子文件-With the Verilog programming language, based on FPGA to achieve the relevant electronic document design 8254
DDRcontroller
- 对DDR控制器的FPGA实现及其代码和参考注释-verilog source code written to read and write DDR
DAC
- 主要实现对DA转换器的控制、调试程序，使用Verilog语言实现其功能-Main achieved control of the DA converter, debugger, use the Verilog language function
ddc
- 电子科大2009-应用于无线电监测的高速信号处理平台设计，软件无线电的DDC的FPGA实现！-UESTC 2009- applies to wireless monitoring of high-speed signal processing platform design, software radio DDC' s FPGA implementation!
FPGAdeguangshanjiancejishu
- 本文档设计了1光栅位移传感器信号的接收、光栅位移传感器信号的整形及电平转换电路设计，用Verilog HDL描述了锁相倍频细分和零位信号处理电路。利用FPGA实现光栅位移系统与上位机接口的电路原理框图-This document designed a grating displacement sensor signal reception, grating displacement sensor signal shaping and level conversion circuit design
dds_project
- DDS直接数字频率合成器，能产生正弦波，方波，锯齿波，三角波四种波形，同时能在12864上显示波形类型和频率，用FPGA verilog实现的-DDS direct digital frequency synthesizer can produce sine, square wave, sawtooth wave, triangle wave four waveform, while in the 12864 on display the waveform type and frequency
SPI_VERILOG
- SPI串行总线接口的Verilog实现.pdf 通过FPGA实现-The Verilog implementation of the SPI serial bus interface. Pdf FPGA implementation
REFRESH
- VERILOG实现数码管动态刷新，开机复位后显示1234-VERILOG digital dynamic refresh, power-on reset is displayed after 1234
shuzishizhong-verilog
- 基于2410开发板数字时钟的开发，实现了计时，日期，跑表的功能-Based on the development of the 2410 development board digital clock, a time, date, stopwatch function
elevator-verilog
- 基于2410开发板控制电梯运行的开发，实现了电梯的基本功能-Development, the basic functions of the elevator control elevator running based on the 2410 development board
digital-Timer
- 数字时钟，使用Verilog实现，已经调试过了-Digital clock, using Verilog implementation
CPU-implementation-in-verilog
- 用verilogHDL实现CPU各项功能-The implementation of CPU funtions based on verilogHDL
fpga-verilog
- 基于fpga-verilog的音频设计，实现音频功能-the fpga-verilog Audio Design
Verilog-Language
- Verilog语言基础知识应用介绍，附加了Quartus9.0逻辑电路的仿真应用以及简单功能实现方法-Verilog language