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ISE
- 是ISE的中文教程，主要是对初学者演示和展示在XILINX的ISE集成软件环境下，如何用VHDL和原理图的方式进行设计输入，用MOdelsim方针。-ISE is a Chinese course is mainly for beginners and display presentation of the ISE in XILINX Integrated Software environment, how to use VHDL and schematic design entry way,
xst
- 赛灵思披露本用户手册，手册，发布说明，和/或specifcation（“文档”）于y欧 仅在外观设计dev的elopment使用操作与赛灵思0712的设备。辎欧不得复制， 分发，重新发布，下载，展示，张贴，或传送的文件以任何形式或通过任何方式 包括但不限于电子，机械，影印，录制，或其他未经事先， 赛灵思公司的书面同意。赛灵思发表任何声明，产生的Y我们的文档使用了。 赛灵思reserv展览服务部的自行决定权，变更，恕不另行通知随时文档。赛灵思
spartan6_fpga_CLB_guide
- xilinx FPGA的CLB高效设计，对提升设计质量很有用-xilinx FPGA' s CLB efficient design, to enhance the quality of design is useful
pBlazIDE36
- There are literally dozens of 8-bit microcontroller architectures and instruction sets.Modern FPGAs can efficiently implement practically any 8-bit microcontroller, and available FPGA soft cores support popular instruction sets such as
DesignandFPGAImplementationof
- In most cases, a bandpass filter characteristic is obtained by using a lowpass-to-bandpass frequency transformation on a known lowpass transfer function. This frequency transformation controls the location of passband edges and transfer zero
FPGAIMPLEMENTATIONOFATUNABLEBANDPASSFILTER
- Any Band-Pass filter may be converted into a tunable filter with a single tuning parameter through the use of a new Tunable Heterodyne Band-Pass Filter concept in which the frequency of the heterodyne signal is adjusted thereby translating the
ppl
- 锁相电路是相位锁定环(Phase Locked Loop)的简称，主要由鉴相器、环路滤波、压控振荡器成 。主要是要掌握LabVIEW图形化编程特点，-PLL circuit is phase-locked loop (Phase Locked Loop) for short, mainly by the phase detector, loop filter, VCO into. Mainly to grasp the features of LabVIEW graphical programm
GeneratingFPGA-AcceleratedDFTLibraries
- 关于DFT的文章，应用FPGA实现傅立叶变换。-Abstract—We present a domain-specific approach to generate high-performance hardware-software partitioned implementations of the discrete Fourier transform (DFT). The partitioning strategy is a heuristic based on the DFT
fpga
- 十分钟学会Xilinx FPGA 设计，是中文版的，比较详细，很容易上手，供大家学习-10 minutes Society of Xilinx FPGA design, is the Chinese version, more detailed, it is easy to use, for everybody to learn ~ ~ ~
dd
- 设计的随机数发生器可产生两个随机数，由一开关（RIN）进行控制，RIN为1时随机数发生器被清除，RIN为0时随机数发生器将产生1-6的两个随机数，可由LED数码管显示，显示的方式可由设计者自行设计，既可以选择数码管中的任两个LED显示随机数，也可让四位LED同时显示一个随机数（按一定的时间跳转显示）。根据给定的材料完成上述系统的设计，用Xilinx ise完成功能的设计与仿真，并最终下载到目标板XILINX SPARTAN-3 Starter Board上进行验证实现。-The random n
Spartan-3E-Starter-User-Guide
- 本文档是XILINX公司生产的FPGA型号为Spartan-3E 芯片内部结构的详细介绍-This document is a XILINX company FPGA model the details of the internal structure of the Spartan-3E chip
phase_test
- VHDL,简易音频数字相位表的设计与实现 数字相位测量仪在工业领域中经常用到的一般测量工具，主要应用与同频率正弦信号间的相位差的测量显示。 本系统采用FPGA实现测量的核心部分，主要由数字鉴相、累加计数器、控制器以及寄存与显示译码电路组成。该系统硬件电路简单，整个系统采用硬件描述语言VHDL作为系统内部硬件结构的描述手段，在XILINX公司的ISE9.1的软件支持下完成。可以对20Hz~20kHz频率范围内的音频信号进行采样鉴相处理，并将数据传回FPGA进行相位差计数累加、测量运算，最后送显
labsolution
- xilinx大学计划完整实验6个。非常值得学习的资料。-This is the xilinx udp labs designed with VHDL.
OZ745
- 4k*2K zynq The OZ745 is a video development platform based around the Xilinx® Zynq-7045 FPGA. The kit includes all the basic components of hardware, design tools, IP, pre-verified reference designs and Board Support Package to rapidly devel
1111
- Xilinx FPGA设计DDR2接口的方法PPT，介绍的非常详细，值得参考。 -Xilinx FPGA DDR2 interface design method PPT, described in great detail, it is worth reference.
LTE-xilinx_PFGA_reference_design
- xilinx中一整套关于LTE在FPGA下的解决方案，里面涉及到LTE设计的L1层和L2层以及结合其硬件的设计方案和内容，非常利于LTE开发-xilinx set on the LTE solution under the FPGA, which relates to the design of LTE L1 and L2 layers and the combination of the hardware design and content development is beneficial
xilinx
- 这是xilinx FPGA的学习ppt 里面详细讲解了具体操作及模块的编写方法-This is xilinx FPGA learning ppt which explain in detail the preparation method and module specific operations
Xilinx
- 使用Xilinx的FPGA开发教程，Xilinx平台主要支持VHDL和Verilog的编程和实现。-Using Xilinx FPGA development tutorial, Xilinx platform is mainly supported by the programming and implementation of VHDL and Verilog.
face-recogn.--in-xilinx-EDK
- it is a approach for implementing face recognition using xilinx EDK .
Xilinx 6 Family2
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