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shizhong-
- 显示时分秒,对小时分钟进行重置,整点报时。-Display minutes and seconds, hours, minutes, reset the whole point of time.
Verilog_HDL
- 多功能数字闹钟设计,具有小时分钟秒功能,整点报时,闹钟响铃-alarm clock
include
- 电路时钟 报时 能够实现计时,以及显示上午或下午的多功能电路-Clock circuit
2014
- 指导教师命题数要求:根据本届毕业生数,平均每位教师学生数约12位学生,教师课题申报时,能满足的学生数控制在15位学生左右,每个课题的学生数一般不超过3位学生-Teachers proposition requirements: according to the number of graduates, the average teacher students about 12 students, teacher grant application, the number of students
