用verilog实现三十二位浮点数算法，通过状态机的方法实现。-32 floating-point implementation using verilog algorithm, the method adopted by the state machine implementation.

按照IEEE 754规定的数值格式，把浮点数转换为十进制显示形式。-According to the values ​ ​ specified in IEEE 754 format floating point numbers to decimal display the form.

介绍DSP中定点数与浮点数的表示形式，比如定点数的Q格式，定点数以及浮点数的运算-Introduced in DSP fixed point and floating-point representation, such as fixed-point Q-format, fixed-point and floating-point operations