搜索资源列表
code_style
- verilog HDL code addtional style for user.
Nop_usb
- A complete presentation of my verilog project. enjoy it. i did it in 4 weeks
Verilog_clk
- Verilog 语言，强大的时钟，可以调时调分，设闹钟等。-Verilog hdl。
dct_verilog
- Implementation of one dimensional Discrete cosine transform using verilog for FPGA implementation
DACTLC5620verilog
- LTC5620的Verilog 代码,采用SPI接口,有详细的描述-Verilog for LTC5620
aaa
- 用verilog vhdl 编写的 38译码器，包括源代码和测试模块-38 decoder
ps2
- verilog PS2键盘解码程序， 之前探讨过PS/2键盘编解码以及数据传输协议，这次自己动手实现了利用FPGA接收键盘编码，然后通过串口传输到PC。做的比较简单，只是通过FPGA把大写字母A-Z转换成相应的ASCII码，只要字母按键被按下，就能在串口调试助手里显示相应大写字母。下面就共享代码吧！ 除了顶层模块，三个底层模块分别为PS/2传输处理模块、串口传输模块以及串口波特率选择模块（下面只给出顶层模块和PS/2传输处理模块的verilog代码）。-verilog PS2 Ke
Copy-of-DIGITAL-VLSI-DESIGN
- a manual for design implementation of fpga and ASIC using verilog
water-level-controller
- water-level controller verilog code for effecient operation of the FSM based water level controller
codes
- verilog code for traffic light controller and test bench for verification purpose
codes
- some basic codes in verilod and thier test benches for understanding the basic verilog codes
examples
- some verilog exersizes with testbenches
FIFO
- FIFO verilog VHDL-FIFO verilog VHDL
VGA_Exp71_1024x768
- 使用quartus编写verilog语言以网球游戏的实现-To use quartus write verilog language to the realization of a tennis game
Motor.asm
- 基于verilog HDL步进电机驱动程序-The verilog HDL stepper motor driver
filter
- verilog—FIR滤波器程序，可移植性强，可以借助FDAtool设计滤波器系数，写到本程序里即可-verilog-FIR filter process, portability, and can make use of FDAtool design filter coefficients, the program can be written to
verilog
- 浅显易懂的vrilogHDL教程，可以帮助你从无到有，快速上手。-Some easy-to-follow vrilogHDL course，which can help you to learn quickly.
CPU
- 基于FPGA控制的ASIC CPU系统设计，全是用VERILOG代码编写，可以做加减乘除运算 -FPGA-based control ASIC CPU system design, all made with VERILOG code writing, arithmetic operations can be done
fpaddmisc-(1)
- VERILOG CODE FOR FLOating point adder
verilog
- 语言设计，虚拟器件，有限状态机，verilong语言教程等-Virtual Appliance