搜索资源列表
CadenceTimingAnalysis
- 使用Cadence进行PCB时序分析好文章，对于学习SI仿真有很大的用处。文章很实用。-Cadence timing analysis a good article, for the rest SI simulation is very useful. Very useful article
FPGA-Timing-Function-Model-Analysis_1
- IR Drop Analysis and Timing-Function Model Generation for Embedded FPGA(I).
FPGA-Timing-Function-Model-Analysis_3
- IR Drop Analysis and Timing-Function Model Generation for Embedded FPGA(III).
verilog-ieee.pdf.tar
- IEEE 2001 verilog 标准 ,详细讲述了 业内 公认的 VERILOG 标准 ,-The Verilog¤ Hardware Descr iption Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstractio
bipeng
- 四冲程发动机进气阀/排气阀避碰计算分析，进行气门可变正时研究，简单实用-Four-stroke engine of intake/exhaust valve anticollision calculation analysis, was studied by means of variable valve timing, simple and practical