搜索资源列表
cy7c68013工作在SLAVE FIFO下的FPGA源代码
- cy7c68013工作在SLAVE FIFO下的FPGA源代码，已经通过，Verilog编写,cy7c68013 slave fifo mode code ,written by hard ware language
UART_spec
- a UART model with FIFO buffer, design with verilog
Cy7C68013_SLAVE-FIFO_Verilog
- 针对CY7C68013在SLAVE FIFO 模式下读写Verilog源代码-For CY7C68013 in the SLAVE FIFO mode to read and write Verilog source code