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DVB
- DVB系统中交织器和解交织器设计的FPGA实现-DVB system, the reconciliation Interleaver Interleaver design FPGA implementation
vhdl
- 行为描述、数据流描述、结构描述实现2to4译码器。-Behavior descr iption, descr iption of the data stream, 2to4 decoder schema.
cpld
- CPLD与电子CAD报告 VHDL中的并行语句、进程 信号、变量、顺序语句 分频器、计数器、译码器、状态机 数字钟综合设计-CPLD and VHDL electronic CAD report in parallel statement, the process signals, variables, sequential statements divider, counter, decoder, an integrated digital clock state machine des
dekoder_el
- VHDL DECODER FOR FPGA
01316017
- investigating the performances and complexities of the various SISO algorithms. a turbo decoder with the selected SISO algorithm is designed and implemented using VHDL as design entry and simulation language