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QC-LDPC-decoder-FPGA
- 文章提出了一种可以兼容不同码率规则和非规则准循环低密度校验码(LDPC)的部分并行译码结构, 用Verilog语言开发，基于该部分并行结构在Altera公司的StratixII-EP2S90器件上验-This paper presents a part of different bit rates can be compatible with the rules and irregular quasi-cyclic low density parity check code (LDPC) de
rs232_des
- uart verilog code using ram and a-uart verilog code using ram and all
apb_slave.v.tar
- apb slave program in verilog
FPGAjiangyi
- 北理工的fpga讲义，不好找，适合verilog学习者-North Institute fpga handouts, easy to find, for verilog learners
dw_apb_rtc_db
- verilog实现rtc文档，可用于实现RTC。-verilog realize rtc document can be used to implement the RTC.
dw_apb_timers_db
- verilog实现timer参考文档，可用于实现timer。-verilog achieve timer reference documentation can be used to implement the timer.
dw_apb_wdt_db
- verilog实现watchdog参考文档，可用于实现watchdog。-verilog realize watchdog reference documentation can be used to implement the watchdog.
443407739SPI_Code(Verilog)
- spi_slave_model tb_spi_top wb_spi_top SPI总线-Please don t borrow random
Verilog VGA显示 W字形
- 利用VGA显示一个W字形 下载到FPGA来连接显示器使用
CAM2006
- Verilog allows you to design your digital design at various abstraction levels.Suppose you have an algorithm to be implemented in the form of a digital circuit then you can easily use Verilog constructs to do the same without worrying about the unde
verilog
- Verilogd的设计练习进阶书籍，可帮助开发人员熟练掌握编程 -Verilogd advanced design practice books, can help developers familiar with programming
VGA全驱动
- 里面有关于FPGA设计的VGA的相应实验说明，以及相关代码
256qam
- Quartus II开发套件，256qam的Verilog仿真，有编码和解码过程-Quartus II，256qam，Verilog，Modem，Demodem
MEM
- hereby i have attached memory controller vip by using system verilog hope this will be helpfule for u
HuaWei-Verilog-
- 华为内部FPGA约束技巧，约束规范，适合新手入门-Huawei within the FPGA constraint techniques, constraint specification, suitable for beginners
coding-style
- 华为FPGA Verilog代码风格，代码规范，适合新手入门-Huawei FPGA Verilog coding style, standardized code, suitable for beginners
Cy7C68013_SLAVE-FIFO_Verilog
- 针对CY7C68013在SLAVE FIFO 模式下读写Verilog源代码-For CY7C68013 in the SLAVE FIFO mode to read and write Verilog source code
DCC2010-FPGA-CPU16ASM-DCC
- cpu verilog 16 bits to control radio software
readmemb_verilog
- 自己总结的，在ise中verilog编程时需要注意的一些细节，主要是readmemb函数用法-Their own summary, in the ise verilog programming need to pay attention to some of the details, mainly readmemb function usage
FpgaFskDemod
- 程序实现一种FSK的解调，语言为verilog。(Program to achieve a FSK demodulation, the language is verilog.)