文件名称:risc8_cpu_verilog
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- 上传时间:2015-12-24
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文件大小:610.69kb
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该实例设计的RSIC-CPU总线结构采用数据线(8位)和指令线(12位)独立分离的哈弗结构,把存储寄存器RAM当做寄存器来寻址使用以方便编程。-The example design of RISC-CPU bus architecture uses a data line (8) and command line (12) is separated with the Harvard architecture, the storage register addressing uses RAM as a register to facilitate programming.
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下载文件列表
risc8/
risc8/alu.v
risc8/basic.rom
risc8/chart/
risc8/chart/Thumbs.db
risc8/chart/图13-11.bmp
risc8/chart/图13-13.bmp
risc8/chart/图13-15.bmp
risc8/chart/图13-16.bmp
risc8/chart/图13-17.bmp
risc8/chart/图13-18.bmp
risc8/chart/图13-20.bmp
risc8/chart/图13-6.bmp
risc8/chart/图13-7.bmp
risc8/chart/图13-9.bmp
risc8/chart/表13-1.bmp
risc8/cpu.v
risc8/cpu_test.v
risc8/dram.v
risc8/exp.v
risc8/idec.v
risc8/pram.v
risc8/regs.v
risc8/risc8.cr.mti
risc8/risc8.mpf
risc8/risc8.vcd
risc8/sindata.hex
risc8/transcript
risc8/vsim.wlf
risc8/wave/
risc8/wave/Thumbs.db
risc8/wave/alu.bmp
risc8/wave/cpu-1.bmp
risc8/wave/cpu-2.bmp
risc8/wave/cpu_test.bmp
risc8/wave/exp.bmp
risc8/wave/idec.bmp
risc8/wave/pram.bmp
risc8/wave/regs.bmp
risc8/work/
risc8/work/_info
risc8/work/alu/
risc8/work/alu/_primary.dat
risc8/work/alu/_primary.vhd
risc8/work/alu/verilog.asm
risc8/work/cpu/
risc8/work/cpu/_primary.dat
risc8/work/cpu/_primary.vhd
risc8/work/cpu/verilog.asm
risc8/work/cpu_test/
risc8/work/cpu_test/_primary.dat
risc8/work/cpu_test/_primary.vhd
risc8/work/cpu_test/verilog.asm
risc8/work/dram/
risc8/work/dram/_primary.dat
risc8/work/dram/_primary.vhd
risc8/work/dram/verilog.asm
risc8/work/exp/
risc8/work/exp/_primary.dat
risc8/work/exp/_primary.vhd
risc8/work/exp/verilog.asm
risc8/work/idec/
risc8/work/idec/_primary.dat
risc8/work/idec/_primary.vhd
risc8/work/idec/verilog.asm
risc8/work/pram/
risc8/work/pram/_primary.dat
risc8/work/pram/_primary.vhd
risc8/work/pram/verilog.asm
risc8/work/regs/
risc8/work/regs/_primary.dat
risc8/work/regs/_primary.vhd
risc8/work/regs/verilog.asm
risc8/work/risc8.vcd
risc8/work/test/
risc8/work/test/_primary.dat
risc8/work/test/_primary.vhd
risc8/work/test/verilog.asm
risc8/alu.v
risc8/basic.rom
risc8/chart/
risc8/chart/Thumbs.db
risc8/chart/图13-11.bmp
risc8/chart/图13-13.bmp
risc8/chart/图13-15.bmp
risc8/chart/图13-16.bmp
risc8/chart/图13-17.bmp
risc8/chart/图13-18.bmp
risc8/chart/图13-20.bmp
risc8/chart/图13-6.bmp
risc8/chart/图13-7.bmp
risc8/chart/图13-9.bmp
risc8/chart/表13-1.bmp
risc8/cpu.v
risc8/cpu_test.v
risc8/dram.v
risc8/exp.v
risc8/idec.v
risc8/pram.v
risc8/regs.v
risc8/risc8.cr.mti
risc8/risc8.mpf
risc8/risc8.vcd
risc8/sindata.hex
risc8/transcript
risc8/vsim.wlf
risc8/wave/
risc8/wave/Thumbs.db
risc8/wave/alu.bmp
risc8/wave/cpu-1.bmp
risc8/wave/cpu-2.bmp
risc8/wave/cpu_test.bmp
risc8/wave/exp.bmp
risc8/wave/idec.bmp
risc8/wave/pram.bmp
risc8/wave/regs.bmp
risc8/work/
risc8/work/_info
risc8/work/alu/
risc8/work/alu/_primary.dat
risc8/work/alu/_primary.vhd
risc8/work/alu/verilog.asm
risc8/work/cpu/
risc8/work/cpu/_primary.dat
risc8/work/cpu/_primary.vhd
risc8/work/cpu/verilog.asm
risc8/work/cpu_test/
risc8/work/cpu_test/_primary.dat
risc8/work/cpu_test/_primary.vhd
risc8/work/cpu_test/verilog.asm
risc8/work/dram/
risc8/work/dram/_primary.dat
risc8/work/dram/_primary.vhd
risc8/work/dram/verilog.asm
risc8/work/exp/
risc8/work/exp/_primary.dat
risc8/work/exp/_primary.vhd
risc8/work/exp/verilog.asm
risc8/work/idec/
risc8/work/idec/_primary.dat
risc8/work/idec/_primary.vhd
risc8/work/idec/verilog.asm
risc8/work/pram/
risc8/work/pram/_primary.dat
risc8/work/pram/_primary.vhd
risc8/work/pram/verilog.asm
risc8/work/regs/
risc8/work/regs/_primary.dat
risc8/work/regs/_primary.vhd
risc8/work/regs/verilog.asm
risc8/work/risc8.vcd
risc8/work/test/
risc8/work/test/_primary.dat
risc8/work/test/_primary.vhd
risc8/work/test/verilog.asm
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