搜索资源列表
Javaserialportdesign
- 一个嵌入式系统通常需要通过串口与其主控系统进行全双工通讯,譬如一个流水线 控制系统需要不断的接受从主控系统发送来的查询和控制信息,并将执行结果或查 询结果发送回主控系统。本文介绍了一个简单的通过串口实现全双工通讯的Java类 库,该类库大大的简化了对串口进行操作的过程。 -An embedded system is usually dominated by its serial port full-duplex communication system, such as a pi
laisoso.cn
- 流水线生产管理系统源代码齐+SQL数据库存-Production management system pipeline source Qi+ SQL data inventory
VLSL-Design-of-High-Performance-Full-search-Block-
- 给出了一种用于H.264变换尺寸全搜索快匹配算法的运动估计电路的改进结构,并完成了VLSI设计。通过脉动阵列和全流水线的设计,达到最高的数据重用率、最小的I/O引脚和100 的硬件计算效率。-An improved architecture for H.264 full-pel motion estimation using variable block size full-search block-matching algorithm is proposed in this paper. To
DLXwhitcache
- 一个DLX流水线CPU的实现 附带一个两级cache的存储层次实现-DLX pipeline a CPU attached to the realization of a two-tier level of cache memory to achieve
analog-to-digitalconversionofthespecificationsandp
- 这份术语表定义了TI公司的delta-sigma、逐次逼近型和流水线模数转换器,并详细说明他们的规格和性能特点。-approximation register (SAR), and pipeline analog-to-digital (A/D) Converter specifications and performance characteristics. Although there is a considerable amount of detail in this docume
cordic
- vhdl语言编写的cordic算法,实现了cordic的流水线运算。-cordic language vhdl algorithm cordic the pipeline operator.
uml
- 你需要加强质量控制的对象是人(敏捷、聪明和有创造性的程序员)--而不是一些集中的流水线机器,或者那些只能胜任简单的、程序化任务的劳动力-You need to strengthen the quality control of the object is (quick, clever and creative programmers)- rather than focus on the pipeline a number of machines, or those who can only do
ADC_parameters_TI_glossary
- TI 官方ADC参数标准术语词汇表。这份术语表汇总定义了TI公司Delte-Sigma技术、逐次逼近存储器(SAR)和流水线(A\D)转换器,并详细说明了他们的规格和性能特点-ADC parameters TI official standard glossary of terms. This table summarizes the definition of the terms of the TI Company Delte-Sigma technology, memory successi
min
- verilog编写的基于并行流水线结构的16阶滤波器的实现-filter
modelsim
- 用verilog编写的基于流水线结构的16阶滤波器的实现 -filter
jiyucontrolNetkongzhirangdezhuangpeiliushuixianjia
- 在罗克韦尔运动控制台上,通过连接在控制网上两台ControlLogix控制器,使用罗克韦尔软件,进行控制网配置、逻辑编程和人机界面组态,实现对装配流水线上生产过程的控制及监视。-On the Rockwell motion console, with 2 ControlLogix controllers connected on ControlNet network, and using Rockwell software to configure network, program ladder
liu_shui
- 流水线设计是高速电路设计中的一个常用设计手段。如果某个设计的处理流程分为若干步骤,而且整个数据处理是“单流向”的,即没有反馈或者迭代运算,前一个步骤的输出是下一个步骤的输入,则可以考虑采用流水线设计方法来提高系统的工作频率。-see up
liushuixian_mul
- 流水线乘法器的VHDL实现,希望对你会有用!-Pipelined multiplier in VHDL implementation, you will want to use!
fir
- 16阶FIR VHDL程序并附带testbench,并有简单流水线设计!-16 Tap FIR vhdl code with testbench and pipelining design
fir_512_378_mux
- 512阶高速FIR成型滤波器,四相位复用,树形加法和多级流水线结构。-512-order high-speed FIR shaping filter, four-phase re-use, tree addition and multi-stage pipeline structure.
CPU
- 32位精简指令处理器 非流水线版 具有无极流水线-32bitRISK CPU without pipeline
liushuixian
- 计算机算法基础流水线调度解决方法,可以参考一下-fundamentals of computer algorithms
MyPlayer
- 结合软件自动生成与流水线的思想实现的课件自动生成软件,是初学者的好帮助!-Combination of software to automatically generate the ideological line of courseware to achieve automatic generation of software is good for beginners help!
DDS
- 分析了 中流水线结构及输入数据在其中移动的特点 提出了一种 流水线结构 给出了实现的方法并作了仿真 分析了对 电路性能的改进方案-DDS
arm7
- ARM7 VERILOG源码,非常精简,3级流水线-ARM7 VERILOG source code, very streamlined, 3-stage pipeline