搜索资源列表
dll11254
- 数字琐相环DPLL的VERLOG代码，MODELSIM下的工程，有测试文件-digital phase-locked loop DPLL VERLOG code MODELSIM under the projects, a test document
fdpll
- 简单的可配置dpll的VHDL代码。 用于时钟恢复后的相位抖动的滤波有很好的效果， 而且可以参数化配置pll的级数。-simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
dpll_4
- 实现4阶数字锁相环，老外写的，有详细注释，如果您觉得不错，就re一下-achieve four bands DPLL, a foreigner writing a detailed notes, if you think it's good, what re
verilogpll
- 用verilog语言编写的全数字锁相环的源代码,基于fpga平台-using Verilog language prepared by the DPLL the source code, they simply based on the platform
PLLprogram
- 数字锁相环程序，适合于FM、AM开发 数字锁相环程序，适合于FM、AM开发-DPLL procedures for FM, AM Development DPLL procedures for FM, AM Development
PLLpro
- 关于数字锁相环的使用，结合FM,AM的使用来说明-DPLL on the use of combined FM and AM to illustrate the use of
010919.pdf
- 全数字锁相环ＶＨＤＬ描述并实现功能仿真，另附有图形说明-DPLL VHDL descr iption and achieve functional simulation, followed by graphic shows
pll_improvement
- 一种改进的全数字锁相环设计 一种改进的全数字锁相环设计-an improved DPLL design an improved design DPLL
VHDLDPLL
- 比较好的技术文章《基于VHDL的全数字锁相环的设计》有关键部分的源代码。-relatively good technical article, "based on VHDL DPLL the design" a key part of the source code.
zicaiyang
- 技术文章《自采样比例积分控制全数字锁相环的性能分析和实现》有一定参考价值-technical article, "Since sampling proportional integral control DPLL performance analysis and achieve" a certain reference value
verilogpll1234
- 基于verilog的全数字锁相环的设计，基于verilog的全数字锁相环的设计。-verilog DPLL the design, verilog based on the DPLL design.
dpll0227
- DPLL同步提取有一定效果-DPLL simultaneously extract a certain effect 11111111111111111111111
chip1
- CPLD的程序,分频,微分等,应用于DPLL -CPLD procedures, frequency, differential, etc. can be applied to DPLL
dpll0226
- 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
DPLL0227+V+qt6
- 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
pll1218
- 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
digital_loopback
- 基于ti公司6713dsp的数字锁相环，运行环境为ccs3.1。希望有所帮助。-ti-based company 6713dsp the DPLL, the operating environment for ccs3.1. Want some help.
060107[1].pdf
- 全数字锁相环,包括ＤＰＤ，ＤＬＦ，ＤＣＯ．-DPLL, including the DPD, DLF, the making.
all_digital_phase_locked_loop
- 一篇关于数字锁相环的很好的文章，费了很大力气才搞到的-a DPLL on the good paper, and a great effort will involve the
changyongmokuai
- 智能全数字锁相环的设计用VHDL语言在CPLD上实现串行通信-DPLL intelligent design using VHDL on the CPLD Serial Communication