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dpll界面程序
- matlab 5.3中菜单unicontrol设计中如何传递变量。本人写了一个非常简单的界面程序，请大家帮忙建评一下一下。-menu design unicontrol how to pass variables. I wrote a very simple interface program, we help build commentary about what.
复件 数字锁相环程序
- 数字锁相环DPLL源程序，用cpld编写，展开后文件比较多，大家请耐心使用。谢谢，多多支持-DPLL source with cpld prepared after the start of more documents, please use patience. Thank you, the generous support!
shuzisuoxiang
- 数字锁相环(DPLL)技术在数字通信、无线电电子学等众多领域得到了极为广泛的应用。与传统的模拟电路实现的PLL相比，DPLL具有精度高、不受温度和电压影响、环路带宽和中心频率编程可调、易于构建高阶锁相环等优点。-Digital phase-locked loop (DPLL) technology in digital communications, radio electronics, and many other fields has been extremely wide range of
FPGAphaselockedloopdesign
- 介绍了应用VHDL技术设计嵌入式全数字锁相环路的方法，详细叙述了其工作原理和设计思想，并用可编程逻辑器件FPGA实现。-Introduce the application of VHDL technical design embedded DPLL road approach, described in detail its working principle and design idea, and programmable logic device FPGA implementation.
dco
- dpll的一个中间器件，实现增量-减量DCO功能-dpll of an intermediate device to achieve incremental- DCO function reduction
DPLL
- pll 的数字实现大家 支持 第一次 传-pll digital impliment
dpll
- All Digital Phase-Locked Loop verilog source code
all_digital_fm_receiver_latest
- Fm receiver using DP-Fm receiver using DPLL
DPLL
- 全数字锁相环的verilog设计，已通过仿真验证能迅速锁定相位-Digital phase loop lock design with verilog
pll
- DPLL由 鉴相器、 模K加减计数器、脉冲加减电路、同步建立侦察电路、模N分频器构成. 整个系统的中心频率(即signal_in和signal_out的码速率的2倍)为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低. -DPLL by the phase detector, K addition and subtraction counter mode, pulse subtraction circuit, sy
dpll
- Digital Phase Locked Loop M-File
dpll_m
- DPLL implementation in matlab
AD-PLL
- 基于VHDL的全数字锁相环的设计与实现，quartusII的仿真程序。-DPLL based on VHDL Design and Implementation, quartusII the simulation program.
dpll
- dpll is used to lock the data
Intelligent-modulus-DPLL-control-design-and-analys
- 智能模值控制的数字锁相环的FPGA设计与分析Intelligent modulus DPLL control design and analysis of FPGA-Intelligent modulus DPLL control design and analysis of FPGA
dpll
- 本工程为锁相环，采用全数字系统设计，输出频率在10M~100M之间！可改进。-This project is phase-locked loop, all-digital system design, the output frequency between the 10M ~ 100M! Can be improved.
dpll
- 数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法-Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis
dpll
- 数字全锁相环的介绍文章，讲述了数字锁相环的实现原理和实现步骤(The introduction of the digital full phase locked loop is introduced, and the realization principle and the implementation steps of the digital phase locked loop are described)
dpll源程序
- 一种设计数字锁相环的思路，包含异或鉴相器、k模可逆计数器、脉冲加减计数器、N分频器等，实现相位的锁定。(A design of digital phase locked loop (PLL) consists of a phase discriminator, a K mode reversible counter, a pulse addition and subtraction counter, a N frequency divider and so on, to lock the pha
载波同步DPLL锁相环路程序
- 载波同步DPLL锁相环路程序，单载波通信项目中的载波同步DPLL锁相环MATLAB程序，并且使用并行化思路去写的，完整有用