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Low-Bit-Rate-Speech-Coding
- Low Bit Rate Speech Coding-- master degr-Low Bit Rate Speech Coding master degree
chapter2-low-bit-rate-speech-coding
- Chapter 2 Low Bit-Rate Speech Coding In this chapter an overview is given of speech coding techniques at several bit rates. Most of them use Linear Prediction. This overview is not meant to be complete its purpose is to make the reader somewhat
ade
- 用VERILOG HDL 语言实现一个8位串行乘法器-VERILOG HDL language with an 8-bit serial multiplier
mult_addtree
- 用VERILOG HDL 语言实现一个4位的流水线乘法器-VERILOG HDL language with a 4-bit pipelined multiplier
bawei
- MATLAB编程源码，可以显示一灰度图像的8个位面图像——bawei.m-MATLAB programming source code, you can display a gray image of the 8-bit plane image- bawei. M
simcoded
- FUNCTION: Simulated Soft-Decision Decoding Bit Error Rate of Hamming-Coded Coherent Binary PSK
slice
- A technique for constructing a processor from modules,each of which processes one bit-field or “slice” of an operand.Bit slice processors usually consist of an ALU of 1,2,4 or 8-bits and control lines including carry or overflow signals usually inter
Task2new
- This prorgam calculates Bit error rate on awgn channel with a particular Eb/No values and plot the graph of BEP(Bit Error Probability) against Eb/No.
6-BIT-count
- 利用AT89S51单片机的T0、T1的定时计数器功能，来完成对输入的信号进行频率计数，计数的频率结果通过8位动态数码管显示出来。要求能够对0－250KHZ的信号频率进行准确计数，计数误差不超过±1HZ。-AT89S51 MCU using T0, T1 of the timer counter functions, to complete the input signal frequency count, counting the frequency of results by 8-bit dy
vhdl1
- vhdl program for 4 bit ripple carry adder using logic gates
MBI5030
- 16-Channel Constant Current LED Driver With 16-bit PWM Control
vhdlcodes1
- vhdl programs for 4 bit ripple carry adder in structural and behavioural modelling
MIMO(MLD)
- This matlab code calculates a bit error rate of MIMO system based on MLD.
adder3
- 此源代码是基于Verilog语言的七人投票表决器 、2 个 8 位数相乘 、8 位二进制数的乘法 、同一循环的不同实现方式、使用了`include 语句的 16 位加法器 、条件编译、加法计数器中的进程、任务、测试、函数、用函数和 case语句描述的编码器、阶乘运算函数、测试程序 、顺序执行、并行执行，特别是七人投票表决器，这是我目前发现的最优的用硬件描述的源代码。-The Verilog language source code is based on the seven-vote, and
codes
- 1: MSE.m : to perform Mean Square Error between 2 images 2: most.m : to get the most redundant value in a matrix 3: getneighbors.m : to get circular neighbors of pixel 4: ColorSpaceConversion.m : convert an image into different color spaces and
64B_adder
- Verilog HDL 64位并行加法器,并且还含有测试文件，可供测试-Verilog HDL 64-bit parallel adder, and also contains a test file, ready for testing
crc-32
- To compute cyclic Redundancy error for 32 bit word
Bit
- 比特分割算法（数字图像的灰度提取）生成txt文件-Bit divided
cla16
- 16位超前进位加法器的源代码，整个工程文件都有，是在ISE10.1下建立的，可以帮助理解超前进位原理（对了，是Verilog的，因为上面没看到只好选VHDL了）-16-bit look-ahead adder the source code files have the whole project was established under the ISE10.1 to help understand the lookahead principle (By the way, is the Ver
dinintex
- The block maps each integer value (or stored integer when you use a fixed point input) to a group of M bits, using the selection for the Output bit order to determine the most significant bit. The resulting output vector length is M times the input v