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Sequencedetector
- 序列检测器可用来检测一组或多组由二进制码组成的脉冲序列信号，这在数字通信领域有广泛的应用。当检测器连续收到一组串行二进制码后，若这组码与检测器中预制的码相同，输出为A，否则输出为B。序列检测I/O口的设计如下：设Din是串行数据输入端，clk是工作时钟，clr是复位信号，D是8位待检测预置数，QQ是检测结果输出端。-Sequence detector can be used to detect one or more sets consisting of binary code from the
ripple_carry_counter
- verilog 语言的简单的4为脉动进位计数器，附带仿真的激励块-verilog language into a simple 4-bit counter for the pulse, with the incentive simulation block
MPEGvariablebitratevideo
- 用MPGE进行压缩编码的变比特率视频流的建模方法介绍和步骤-MPGE compression with variable bit rate encoded video stream modeling methods and steps for introduction
modelbasedonfulllengthVBRMPEG4videotraces
- 全长变比特率基于MPGE压缩编码的视频流的源建模方法及知识的详细介绍-Full variable bit-rate coding based on video streaming MPGE source modeling methods and a detailed descr iption of knowledge
1602
- AVR单片机控制1602液晶显示屏，4位数据口传送，从右向左滚动显示“I Like AVR”等-1602 LCD AVR MCU Control, 4-bit data port transfer, from right to left scrolling shows " I Like AVR" , etc.
ALU
- Write an 8085 ALP to design a 4-bit ALU. The ALU should be able to perform addition, subtraction, AND operation, OR operation on 4-bit inputs based on the desired operation
avrlcd_4bit
- source code for interfacing avr microcontroller with 16x2 lcd in 4 bit mode
ALU_32
- 32 bit ALU design,LU Operations: This input specifies the ALU operation to be used during the acquisition process. The ALU operations are divided into logical operations and two classes of arithmetic operations. The two classes of arithmetic operatio
lab7
- 在這個實習當中，我們學習利 用 Hierarchical VHDL code 的方式，來 實現一 個n-bit 的ripple-carry adder，並學習使用package。-In this practice among the profit we can learn to use Hierarchical VHDL code the way to achieve an n-bit future of the ripple-carry adder, and lea
16bit_pipeline
- 16 bit pipeline design by vhdl.
huffmantree
- Huffman code tree generation with a given input bit stirng
MATLAB_digital_modulation
- 设定噪声为高斯白噪声，对2ASK、2FSK、2PSK、2DPSK等各种调制方式及相应的主要解调方式下（分相干与非相干）的误码率进行统计，并与理论值进行比较，以图形方式表示误码率与信噪比间的关系。 -Set the noise is Gaussian white noise, right 2ASK, 2FSK, 2PSK, 2DPSK a variety of modulation and corresponding demodulation mode, the main (sub-coher
decodeBitFlip
- ldpc bit flipping decoding in matlab
Alu-4bit
- alu 4 bit with verilog in modelsim and work correct
PCA953
- pca953 control firmware pca953 is 8-bit i2c-bus and SMBus low power I/O port with interrupt and reset
OFDM_sync
- Matlab的OFDM在多径Rayleigh信道下的同步 1. 假设频率已同步，设计OFDM一种具体的采用循环前缀进行时间同步方法，用Simulink进行仿真，画出比特信噪比与捕获概率的关系曲线。 2. 设时间已同步，设计OFDM一种具体的采用循环前缀进行频率同步方法，用Simulink进行仿真，画出比特信噪比与频率同步误差的关系曲线.-Matlab-OFDM in multipath Rayleigh channel synchronization 1. Assume th
Chapter11-13
- 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个
MANIK
- MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed below. Features Hardware Features • Data Path Width 32 bits, with Four stage pipeline. • Mixed 16/32 bit instructions for code density ̶
Bitplanedecomposition(matlab)
- Using matlab bit plane decomposition. It contained 2 versions. One is using functions. One is using matlab codes.
8bit_RISC_CPU_RTL_Code
- 8位RISC CPU 内核源码(VERILOG版)-8 bit RSIC CPU RTL code(Verilog)