搜索资源列表
fifo123456
- 16*16位的先进先出队列FIFO程序,可作参考-16* 16-bit FIFO queue FIFO procedures, can be used for reference
8-bit_multiplier
- 用ASM原理做二進位8-BIT乘法的乘法器，內附範例的輸入檔。-ASM to do with the principle of binary multiplication of 8-BIT multiplier, the input file containing a sample.
T3_1
- 一个4比特移位寄存器,活跃在不断上升的边缘的时钟。登记应能转移左、右移,接受连续剧和平行(负荷)输入,而有一个异步预设(“1111”)和清晰的(“0000”)的能力。-a 4-bit shift register which is active on the rising edge of the clock. The register should be able to shift left, shift right, accept a serial and parallel (load) i
CRC
- 本文提出一种通用的CRC 并行计算原理及实现方法,适于不同的CRC 生成多项式和不同并行度(如8 位、16 位、及32 位等) ,与目前已采用的查表法比较,不需要存放余数表的高速存储器,减少了时延,且可通过增加并 行度来降低高速数传系统的CRC 运算时钟频率.-In this paper, a universal principle of CRC and implementation of parallel computing methods for generating differ
jiao2
- 此代码为用比特填充法编写的ldpc码的校验矩阵。它的girth为6，最大行重为8，列重为3-This code with bit-filling method for the preparation of the calibration matrix ldpc code. Its girth is 6, maximum line weight of 8, out of 3 re-
HOS_MIMO
- 基于二阶和高阶统计量的MIMO系统盲信道估计，可完美进行信道估计，进行误码率及误差分析等。-Based on second-order and higher-order statistics of the MIMO system, blind channel estimation can be the perfect channel estimation carried out for the bit error rate and error analysis.
8-bit-Multiplier
- 一种基于加法器树方法的8为乘法器的VHDL源码，该方法虽然相对占有资源多，但仿真快-VHDLSourceProgramof8-bit-Multiplier
adder17
- 实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binary output of the adder 17, and
8risc
- 8位RISC CPU,包括alu,count,machine-8 bit risc cpu
8bit_adder_AND_4x4_Multiplier
- 位加法器的verilog程序与4×4 乘法器的verilog描述-Verilog-bit adder of the procedures and 4 × 4 multiplier verilog descr iption! ! !
D016057
- RA 码及其在通信系统中的应用研究确良：重复累积码；简化译码算法；高斯估计；比特交织编码调制；光纤通 信；码率兼容码；Turbo 码交织器-RA Code and Its Application in Communication System does good: repeat accumulate codes simplify the decoding algorithm Gaussian estimation Bit-Interleaved Coded Modulation op
BitVector
- 一个进行按位存储的容器，BitVector，位向量。可以根据加入的数据自动改变容器大小，提供方便的访问接口。-Carried out by a digital storage containers, BitVector, bit vector. Automatically change the container s size when data be added, provide convenient access interface.
ADDER
- 本设计是用32位的并行全加器的,可以实现浮点运算!-The design is a parallel 32-bit full adder, and floating-point operations can be achieved!
IEEE_754_Floating_Point_Conversion_from_32_bit_He
- conversion From 32-bit Hexadecimal Representation To Decimal Floating-Point Along with the Equivalent 64-bit Hexadecimal and Binary Patterns
Convolutional_Qam16_soft_awgn
- Convolutional 16QAM 3 bit soft decision and viterbi decoding
RAM
- 这是用51单片机将数据写进ram62256中的程序+proteus仿真，另外还用8位led同时宣示八位二进制数！希望能够对单片机爱好者有所帮助！-This is a single chip using 51 data included in the ram62256 procedures+ proteus simulation, also led by an 8-bit binary number at the same time declaring eight! Single-chip lov
figure0206
- UWB接收机TR方案，仿真程序，误码率小-UWB receiver TR program, simulation program, a small bit error rate
bijiaoqi
- pci 32位的core的实现源代码，我晕阿，实在是不好怎么说阿-pci 32-bit core of the realization of the source code, I fainted Ah, how to say it is not Arab. . . .
AdderSubtractor
- 4-Bit Adder Subtractor Verilog Code. (Complete project)
4_Bit_Alu_vhdl
- Complete VHDL Code for a 4 BIT ALU PROJECT